Tapered Storage Node Contact Plug for Semiconductor Devices
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Solution Overview
Problem
In semiconductor devices with buried gates, the use of isolation gate structures leads to increased leakage current and contact resistance due to the challenges in patterning bit line contacts and forming storage node contacts, particularly when using trench-type device isolation films.
Innovation Solution
The implementation of a semiconductor device with a damascene bit line process, where the upper part of the storage node contact plug is enlarged, and a tapered configuration is used to increase the overlap area with the storage node, reducing contact resistance and improving device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a trench-type device isolation film is used in a buried gate structure, then device isolation is improved, but leakage current increases and contact resistance increases
Solution Approach 1:
The patent applies local quality by forming a tapered configuration specifically at the upper part of the storage node contact plug, rather than uniformly throughout the entire structure. This localized geometric modification increases the overlap area between the contact plug and storage node in the critical region where contact resistance matters most, while maintaining the trench-type isolation film's isolation effectiveness in other regions.
Solution Approach 2:
The patent changes the geometric parameter of the storage node contact plug from a cylindrical shape to a tapered shape, where the diameter varies along the length. This parameter change increases the surface area of overlap with the storage node, thereby reducing contact resistance without altering the trench-type isolation film structure that provides device isolation.
2Productivity
If the contact hole size is reduced to increase storage node contact density, then productivity is improved, but patterning precision deteriorates and short-circuiting occurs
Solution Approach 1:
The patent transitions from a two-dimensional contact hole pattern to a three-dimensional tapered structure. By utilizing the vertical dimension and creating a tapered shape that widens toward the top, the patent increases the effective contact area without increasing the footprint area, thereby maintaining high density while improving manufacturability and reducing short-circuit risks.
3Ease of manufacture
If the damascene bit line process is used to form storage node contacts, then ease of manufacture is improved, but contact resistance increases due to reduced contact area
Solution Approach 1:
The patent modifies the geometric parameters of the storage node contact plug by implementing a tapered configuration. This changes the contact area parameter from a small constant cross-section to a progressively increasing area, thereby reducing contact resistance while maintaining compatibility with the damascene bit line process flow.
Data Source
AI summary
A semiconductor device and a method for manufacturing the same are disclosed. In the semiconductor device, an upper part of a storage node contact plug is increased in size, and an area of overlap between a storage node formed in a subsequent process and a storage node contact plug is increased, such that resistance of the storage node contact plug is increased and device characteristics are improved. The semiconductor device includes at least one bit line formed over a semiconductor substrate, a first storage node contact plug formed between the bit lines and coupled to an upper part of the semiconductor substrate, and a second storage node contact plug formed over the first storage node contact plug, wherein a width of a lower part of the second storage node contact plug is larger than a width of an upper part thereof.