Tapered Subfin FINFET Traps Lattice Defects
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Solution Overview
Problem
Traditional FINFET transistors face challenges in reducing lattice defects that increase resistivity and hinder high-speed performance due to aspect ratio trapping, which complicates manufacturing and affects structural integrity and leakage currents.
Innovation Solution
A FINFET transistor with a tapered subfin structure is designed, where the sidewalls are tapered inward to trap lattice defects, reducing their propagation into the channel and simplifying manufacturing processes by eliminating complex etching dynamics, thereby enhancing structural stability and reducing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional vertical subfin structure is used, then manufacturing process is simpler, but lattice defects propagate into the channel increasing resistivity and reducing transistor speed
Solution Approach 1:
The patent applies asymmetry by transitioning from a traditional vertical subfin structure to a tapered subfin structure with different angles (α and β) on opposite sides. This asymmetric geometry creates non-uniform stress distribution and modifies defect propagation paths, enabling lattice defects to be trapped away from the channel region while maintaining manufacturing feasibility through controlled epitaxial growth parameters.
Solution Approach 2:
The patent utilizes parameter changes by adjusting the taper angles (α and β) of the subfin structure to optimize defect trapping. By varying these geometric parameters during the epitaxial growth process, the invention controls the aspect ratio and stress distribution to prevent defect propagation into the channel, thereby improving transistor speed without excessive structural complexity.
2Reliability
If tapered subfin structure is implemented, then lattice defects are trapped and transistor performance improves, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-defining the tapered subfin geometry through controlled epitaxial growth before subsequent processing steps. The taper angles (α and β) are established during the initial subfin formation, which pre-determines the defect trapping behavior and stress distribution. This preliminary structural configuration simplifies later manufacturing steps by eliminating the need for complex post-processing etching to achieve the desired defect-trapping geometry.
3Ease of manufacture
If vertical subfin structure is used, then manufacturing is simpler, but leakage currents are higher due to defect propagation
Solution Approach 1:
The patent converts the harmful effect of lattice defects into a beneficial outcome by designing the tapered subfin structure to actively trap defects. Instead of attempting to eliminate defects entirely, the invention utilizes the inherent defect-generating epitaxial growth process to create a geometry where defects naturally accumulate in the tapered regions away from the channel. This converts the harmful defect propagation into a beneficial defect-trapping mechanism that reduces leakage currents while maintaining manufacturing simplicity through standard epitaxial techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The tapered subfin structure effectively reduces lattice defects in the channel, improving transistor speed, stability, and manufacturing efficiency while minimizing leakage currents and allowing for the use of the same material for the subfin and channel, leading to faster and more reliable devices with reduced manufacturing complexity.
Implementation Method 1
a tapered subfin structure having a sidewall surface area that is large enough to induce aspect ratio trapping of lattice defects along sidewalls of the subfin structure so that the defects are substantially prevented from reaching said FINFET transistor's channel
Data Source
AI summary
An apparatus is described. The apparatus includes a FINFET transistor. The FINFET transistor comprises a tapered subfin structure having a sidewall surface area that is large enough to induce aspect ratio trapping of lattice defects along sidewalls of the subfin structure so that the defects are substantially prevented from reaching said FINFET transistor's channel.