Tapered Switch Width for Resistor-Ladder DAC Settling Time
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Solution Overview
Problem
In high-frequency integrated circuits, the reduced power supply voltage challenges the performance of Digital to Analog Converters (DACs) due to increased settling time and resistance issues with MOS transistors, particularly in resistor-ladder DACs, as the voltage headroom decreases, making it difficult to maintain large signal swings and efficient switching.
Innovation Solution
A tapered-switch width structure for the resistor ladder DAC is implemented, increasing the p-channel transistor width from 2 um to 5 um in consecutive groups as the tap voltage drops from 1.2 V to 0.7 V, minimizing switch parasitic capacitance and on-resistance, thereby reducing the maximum settling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the power supply voltage is reduced to reduce leakage and save power, then power consumption is reduced, but the settling time of the DAC increases and signal swing capability deteriorates
Solution Approach 1:
The patent applies local quality by making the switch widths non-uniform across different voltage taps. Specifically, switches connected to lower voltage taps (e.g., mid-Vdd region) have larger widths to compensate for higher on-resistance, while switches at higher voltage taps have smaller widths. This localized adjustment optimizes the RC time constant at each tap position, maintaining fast settling times across the entire voltage range even with reduced supply voltage.
Solution Approach 2:
The patent changes the physical parameter of switch width to optimize performance. By varying the switch width parameter across different taps rather than using uniform widths, the design achieves better control over on-resistance and settling time. The width parameter is specifically adjusted to maintain acceptable RC time constants despite the reduced voltage headroom.
2Ease of manufacture
If uniform switch width is used in the DAC switch array, then manufacturing is simplified, but settling time increases due to higher on-resistance at mid-Vdd taps
Solution Approach 1:
The patent implements local quality by assigning different switch widths to different tap positions based on their specific electrical characteristics. Switches at mid-Vdd taps where on-resistance is naturally higher are given larger widths to compensate, while switches at other positions use smaller widths. This non-uniform distribution optimizes the overall settling performance without requiring complex manufacturing processes.
3Reliability
If larger switch size is used to reduce on-resistance, then signal swing capability is improved, but switch parasitic capacitance increases which dominates node capacitance
Solution Approach 1:
The patent applies local quality by making switch width a variable parameter rather than a constant. Each switch's width is locally optimized based on its position in the resistor ladder and the voltage level it handles. This prevents the uniform increase in parasitic capacitance that would result from simply scaling up all switches, while still providing sufficient drive capability at critical tap positions.
Solution Approach 2:
The patent introduces dynamics by making the switch width parameter position-dependent rather than static and uniform. The switch width dynamically adapts to the specific requirements of each tap position, creating an optimized distribution that balances on-resistance and parasitic capacitance effects across the entire DAC output range.
Data Source
AI summary
One of the critical design parameters occurs when a digital signal is converted into an analog signal. As the supply voltage drops to less than 2 times of threshold voltage to reduce leakage and save power, generating a relative large swing with a resistor-ladder DAC becomes more difficult. For a 5 bit DAC, 32 sub-arrays are used to select the appropriate voltage from the series coupled resistor network. Each sub-array uses p-channel transistors where the sub-array extracting the lowest voltage 700 mV only has a 100 mV of gate to source voltage. To compensate for the reduced gate to source voltage, the sub-arrays are partitioned into four groups. In each group, the p-channel width is increased from 2 um to 5 um, as the tap voltage drops from 1.2 V to 0.7 V. This allows the p-channel transistor with a small gate to source voltage to have a larger width thereby improving performance.