Tapered Through Package Vias for Semiconductor Packaging

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Solution Overview

Problem

The semiconductor industry faces challenges in packaging semiconductor devices due to the need for smaller, more densely integrated components, which requires innovative methods for forming through package vias (TPVs) that offer controlled height and reduced packaging costs and time.

Innovation Solution

The method involves forming a conductive material over a carrier wafer, patterning it using photoresist to create tapered through package vias (TPVs) with specific dimensions, and coupling a semiconductor device to the carrier wafer, followed by the formation of a redistribution layer (RDL) and subsequent packaging steps, including molding, debonding, and singulation, to achieve efficient and cost-effective packaging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional packaging methods are used, then packaging is simpler, but TPV height control is poor and packaging time is longer

Engineering Contradiction:

ImproveTPV height controlVSAvoidpackaging throughput

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies preliminary action by forming the conductive material layer and patterning it into TPV structures before mounting the semiconductor die. This preliminary formation of conductive pathways enables precise height control of TPVs while streamlining subsequent packaging steps, thereby improving both manufacturing precision and productivity

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent segments the packaging process into distinct stages: forming conductive material layers, patterning TPVs, mounting dies, and forming RDLs. This segmentation allows each step to be optimized independently, achieving precise TPV height control through controlled deposition and etching while maintaining efficient overall packaging throughput

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If integrated circuit density is increased, then more components are integrated, but package area must be reduced

Engineering Contradiction:

Improvecomponent integration densityVSAvoidpackage area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent transitions from two-dimensional planar interconnection to three-dimensional vertical interconnection through the formation of through-package vias (TPVs) that extend through the substrate thickness. This dimensional change enables higher component integration density by utilizing vertical space, allowing more components to be interconnected within a reduced package footprint

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nesting by placing multiple conductive material layers and TPV structures within the substrate thickness, creating a nested three-dimensional interconnection architecture. This nested structure enables dense integration of multiple components by efficiently utilizing the vertical dimension within the package volume

Inventive Principle:

Principle #7Nested doll (Nesting)

3Manufacturing precision

If TPVs are formed with precise height control, then manufacturing precision improves, but process complexity increases

Engineering Contradiction:

ImproveTPV height controlVSAvoidpackaging process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent controls TPV height by precisely controlling deposition parameters (thickness, composition) and etching parameters of the conductive material layers. By adjusting these parameters, the TPV height is controlled to correspond to the thickness of the semiconductor die, achieving precise height control through parameter optimization rather than complex process steps

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces mechanical height adjustment methods with controlled material deposition and removal processes. Instead of mechanically adjusting TPV height, the invention uses controlled deposition of conductive materials and selective etching to achieve precise height control, simplifying the overall process while maintaining high precision

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in packaged semiconductor devices with controlled TPV height, reduced packaging costs, and faster throughput, minimizing yield loss and simplifying manufacturing processes.

Implementation Method 1

patterning the conductive material using the patterned layer of photoresist as an etch mask to form a plurality of through package vias (TPVs)

Methodology Applied

Scientific EffectEtching:

Data Source

PatentUS9847315B2Packages, packaging methods, and packaged semiconductor devices

Publication Date: 2017.12.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a redistribution layer (RDL) and a plurality of through package vias (TPV's) coupled to the RDL. Each of the plurality of TPV's comprises a first region proximate the RDL and a second region opposite the first region. The first region comprises a first width, and the second region comprises a second width. The second width is greater than the first width.