Tapered Through Semiconductor Via for Hybrid Bonding Alignment
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly due to issues such as metal dishing and misalignment during the fabrication process.
Innovation Solution
A semiconductor device design featuring a through semiconductor via with a tapered sidewall and a hybrid bonding process, where the first and second semiconductor structures are topologically aligned and bonded, with an insulation layer and a thermal dissipation layer, to reduce series resistance and defects like metal dishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If semiconductor devices are scaled down to improve computing ability, then device density and integration are improved, but manufacturing precision and reliability deteriorate due to metal dishing and misalignment issues
Solution Approach 1:
The patent applies preliminary action by forming a tapered sidewall structure in the through semiconductor via before filling it with conductive material. This tapered structure is created in advance to compensate for potential misalignment issues during subsequent bonding and filling processes, ensuring that the via maintains proper alignment and electrical connection even when scaling down device dimensions.
Solution Approach 2:
The patent changes the geometric parameters of the through semiconductor via by creating a tapered sidewall with a specific angle (e.g., 5-15 degrees from vertical). This parameter change in the via geometry helps to reduce metal dishing during electroplating and improves alignment tolerance, allowing for successful scaling while maintaining manufacturing precision.
2Reliability
If through semiconductor via is used to improve electrical connection, then series resistance is reduced, but device complexity increases due to additional fabrication steps
Solution Approach 1:
The patent merges multiple functions into the through semiconductor via structure. The via serves simultaneously as an electrical connection path, a structural support element, and a thermal management conduit. The tapered sidewall formation is combined with the bonding process, reducing the need for separate alignment and support structures, thereby managing complexity while maintaining reliable electrical connections.
3Manufacturing precision
If main bonding layers are made coplanar with circuit layers to simplify bonding, then bonding alignment is improved, but series resistance increases due to longer current path
Solution Approach 1:
The patent resolves this contradiction by transitioning from a two-dimensional coplanar bonding approach to a three-dimensional tapered via structure. The via extends vertically through the bonding interface with a tapered sidewall, allowing the bonding layers to remain coplanar for alignment simplicity while the via provides a direct, low-resistance electrical path through the vertical dimension, thus reducing the current path length despite the coplanar configuration.
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, a through semiconductor via, and an insulation layer. The first semiconductor structure includes a first circuit layer and a first main bonding layer in the first circuit layer and substantially coplanar with a front face of the first circuit layer. The second semiconductor structure includes a second circuit layer on the first circuit layer and a second main bonding layer in the second circuit layer, and topologically aligned with and contacted to the first main bonding layer. The through semiconductor via is along the second semiconductor structure and the first and second main bonding layer, and extending to the first circuit layer. The insulation layer is positioned on a sidewall of the through semiconductor via.