Tapered Through-Substrate Via Structure for Void-Free Filling
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Solution Overview
Problem
Existing through-substrate via structures face issues with voids inside the conductive layer and uneven surface planarization due to different material properties and stress distribution during the back grinding process, leading to protrusion of the conductive layer and potential scratching.
Innovation Solution
A through-substrate via structure with a tapered through hole and a semiconductor layer interposed between the conductive layer and the semiconductor substrate, where the semiconductor layer is formed on the sidewall and bottom surface of the hole, and the conductive layer is filled within, with a planarization process to ensure even surface coplanarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a through hole is formed in the semiconductor substrate to create a through-substrate via structure, then signal transmission speed and chip stacking density are improved, but voids are produced inside the material filling the through hole
Solution Approach 1:
The through hole is designed with a tapered shape rather than a cylindrical shape, creating an asymmetric geometry where the hole width varies along its length. This asymmetric design allows the conductive material to fill more uniformly from the wider opening toward the narrower bottom, preventing void formation while maintaining the through-substrate via functionality for high-speed signal transmission
2Manufacturing precision
If the planarization process is performed on the bottom surface of the semiconductor substrate, then surface flatness is improved, but the conductive layer protrudes outside the through hole due to uneven stress distribution and different etching selectivity
Solution Approach 1:
A semiconductor layer is selectively formed only at the bottom surface of the through hole, creating a local structural modification. This localized addition of material provides stress compensation precisely where needed, preventing the conductive layer from protruding during planarization while maintaining surface flatness, without requiring global changes to the entire substrate structure
Solution Approach 2:
The semiconductor layer acts as an intermediary between the conductive layer and the substrate, mediating the stress distribution during the planarization process. This intermediate layer has etching selectivity matching the substrate, allowing it to be removed uniformly during planarization while protecting the conductive layer from protrusion, thus eliminating the harmful protrusion effect
3Adaptability or versatility
If materials with different properties are used inside and outside the through hole, then the through-substrate via structure can be formed, but uneven stress distribution occurs during the back grinding process
Solution Approach 1:
The semiconductor layer is made of the same material as the substrate, creating material homogeneity at the interface region. This homogeneity ensures that both the semiconductor layer and substrate have identical etching selectivity to the grinding fluid, allowing them to be removed uniformly during the back grinding process and eliminating uneven stress distribution, while still enabling the through-substrate via structure to be formed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces voids inside the conductive layer and prevents protrusion, achieving a flat and even semiconductor substrate surface by matching the etching selectivity of the semiconductor layer and substrate materials, thereby minimizing stress distribution issues and potential scratching.
Implementation Method 1
The production of the voids inside the material filling the through hole can be reduced by the through hole with a tapered angle
Implementation Method 2
different etching selectivity to the grinding fluid
Implementation Method 3
performing the planarization process on the bottom surface of the semiconductor substrate
Implementation Method 4
the conductive layer in the through hole may protrude outside of the semiconductor substrate because of uneven stress distribution
Data Source
AI summary
A semiconductor device includes a through-substrate via structure, a first metal layer, an electronic component over the through-substrate via structure, a second metal layer and another electronic component below the through-substrate via structure. The through-substrate via structure includes a through hole penetrating from a first surface to an opposite second surface of a semiconductor substrate, and an acute angle is included between a sidewall of the through hole and the second surface on a side of the semiconductor substrate. The through-substrate via structure also includes a conductive layer that fills the through hole, and a semiconductor layer disposed in the through hole and interposed between the conductive layer and the semiconductor substrate.