Tapered Through-Via Packaging to Prevent Planarization Defects
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Solution Overview
Problem
The semiconductor industry faces challenges in creating smaller and more efficient packaging techniques for semiconductor dies, particularly in avoiding defects during planarization processes in Package-on-Package (POP) technology.
Innovation Solution
The formation of through vias with tapered upper portions and convex topmost surfaces, achieved through multiple plating processes with increasing plating current densities, helps avoid defects during subsequent planarization processes by reducing the amount of conductive material ground and redistributing forces evenly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through vias are formed with conventional plating processes, then manufacturing simplicity is maintained, but defects occur during planarization processes
Solution Approach 1:
The plating process is segmented into multiple sequential stages, each with different current densities. The first stage uses a first current density to deposit initial conductive material, and the second stage uses a second current density (higher than the first) to deposit additional conductive material, creating a composite via structure with optimized mechanical properties for planarization
Solution Approach 2:
The plating current density parameter is changed between stages. The process transitions from a lower current density in the first stage to a higher current density in the second stage, resulting in conductive material layers with different microstructures and mechanical characteristics that collectively prevent planarization defects
2Stability of the object's composition
If uniform plating is applied throughout the via, then manufacturing simplicity is maintained, but mechanical stability during planarization is reduced
Solution Approach 1:
Different regions of the through via receive different plating conditions. The lower portion of the via is plated with a first current density producing one material characteristics, while the upper portion is plated with a second current density producing different material characteristics, optimizing each region for its specific mechanical requirements during planarization
3Productivity
If high current density plating is used throughout, then plating speed is improved, but void formation in encapsulant increases
Solution Approach 1:
The plating process is divided into two stages: a first stage with lower current density that deposits conductive material more slowly with better void elimination, and a second stage with higher current density that rapidly deposits the remaining conductive material. This segmentation allows the lower portion to be filled carefully while the upper portion is filled quickly
Solution Approach 2:
The first plating stage performs a preliminary action by depositing a foundation layer of conductive material with lower current density, preparing the via structure to prevent void formation. This preliminary layer then serves as the base for the second stage high-speed plating
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the mechanical stability of the package component, reduces the chances of shorting the through vias, and improves manufacturing yield by minimizing void formation in the encapsulant during planarization.
Implementation Method 1
multiple plating processes with increasing plating current densities
Data Source
AI summary
In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.