Tapered Through-Via Structure for Stable MBCFET Substrates

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Solution Overview

Problem

Existing semiconductor devices face challenges in maintaining substrate thickness stability during the formation of through-vias, which affects the connectivity and reliability of multi-bridge channel field effect transistors (MBCFETs).

Innovation Solution

The semiconductor device design includes a substrate with a first through-via having a width that continuously reduces as it approaches the lower surface, ensuring stable connection with a second through-via, and utilizing an insulating liner to maintain electrical insulation and structural integrity, while the upper and lower surfaces of the through-via are formed on the same plane as the substrate surfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a through-via is formed with a constant width throughout its length, then the manufacturing process is simpler, but the substrate thickness stability deteriorates and connection reliability decreases

Engineering Contradiction:
Improvethrough-via formation processVSAvoidconnection reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The through-via is designed with an asymmetric width profile where the width varies along its length, being wider at the upper portion and narrower at the lower portion. This asymmetric geometry provides mechanical support to the substrate, maintaining substrate thickness stability while ensuring reliable connection between conductive layers, thereby resolving the contradiction between manufacturing simplicity and connection reliability.

Inventive Principle:
Principle #4Asymmetry

2Stability of the object's composition

If the through-via width is reduced near the lower surface, then substrate thickness stability improves, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvesubstrate thickness stabilityVSAvoidthrough-via width control
Core Design Contradiction:
Stability of the object's compositionVSManufacturing precision

Solution Approach 1:

The through-via width transitions smoothly with a curved profile rather than abrupt changes. The width continuously decreases from the upper to lower surface, creating a tapered or rounded geometry that reduces stress concentrations and provides gradual mechanical support. This curved transition maintains substrate thickness stability while being more tolerant to manufacturing variations compared to sharp geometric changes.

Inventive Principle:
Principle #14Spheroidality (Curvature)

3Reliability

If the through-via width is increased at the upper surface, then connection stability with upper layers improves, but the device complexity increases

Engineering Contradiction:
Improveconnection stabilityVSAvoidthrough-via geometry
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The through-via exhibits local quality variations where different sections have different widths optimized for their specific functions. The upper portion has a wider width to ensure stable connection with upper conductive layers and provide adequate contact area, while the lower portion narrows to provide mechanical support to the substrate. This localized optimization of geometry at different positions achieves both connection stability and substrate support without requiring complex multi-component structures.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240339379A1Semiconductor device
Publication Date: 2024.10.10 SAMSUNG ELECTRONICS CO LTD
  • US20240339379A1 patent drawing
  • US20240339379A1 patent drawing
  • US20240339379A1 patent drawing

AI summary

A semiconductor device includes a substrate, a first active pattern extending in a first horizontal direction, a second active pattern extending in the first horizontal direction and spaced apart from the first active pattern in a second horizontal direction, a gate electrode extending in the second horizontal direction, a source/drain region disposed on a side of the gate electrode, a first through-via disposed inside the substrate between the first and second active patterns, an upper interlayer insulating layer covering the source/drain region, and a second through-via connected to the first through-via by passing through the upper interlayer insulating layer in a vertical direction spaced apart from the source/drain region in the second horizontal direction. A width of the first through-via in the second horizontal direction is continuously reduced as the first through-via becomes adjacent to the lower surface of the substrate.