Low Resistance Through-Wafer Via with Tapered Constriction
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Solution Overview
Problem
Conventional through-wafer vias in microelectronics and MEMS face challenges with high resistance and incomplete conductive material coverage due to shadowing effects during physical vapor deposition, especially for narrow and deep via holes, limiting their reliability and efficiency.
Innovation Solution
The introduction of a through-wafer via design featuring a constriction with sloping sidewalls that widens towards the opening, allowing for improved conductive material coverage and adhesion, which is achieved through a combination of anisotropic etching and conductive coating deposition, enhancing the reliability and thermal properties of the vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical vapor deposition is used to deposit conductive material on vertical sidewalls of narrow and deep via holes, then the deposition process is simple, but the shadowing effect causes incomplete coverage and high resistance
Solution Approach 1:
The patent applies asymmetry by transforming the symmetric vertical sidewall geometry into an asymmetric tapered geometry. The via holes are designed with sloping sidewalls that angle inward from the opening toward the bottom, creating an asymmetric shape that eliminates shadowing effects during physical vapor deposition. This asymmetric geometry ensures that the deposition source can directly illuminate all sidewall surfaces, achieving complete and uniform conductive material coverage without the resistance problems associated with vertical sidewalls.
Solution Approach 2:
The patent employs parameter changes by modifying the geometric parameters of the via holes. Specifically, the sidewall angle is changed from vertical (90 degrees) to a tapered angle (e.g., 70-85 degrees from vertical), and the diameter is varied along the depth of the via. This parameter transformation optimizes the geometry for physical vapor deposition, ensuring that all sidewall surfaces are accessible to the deposition flux while maintaining structural integrity and low resistance.
2Reliability
If wire bonding is used to interconnect stacked devices, then the process is well-established, but it requires large space, long leads, and gives high resistance
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar interconnection (wire bonding on the surface) to three-dimensional through-wafer interconnection. Instead of using long external leads that extend across the packaging surface, the invention creates direct vertical pathways through the wafer substrate itself. This dimensional transformation allows electrical connections to be made directly between stacked devices through the thickness of the wafer, eliminating the need for long external leads and complex surface packaging arrangements.
Solution Approach 2:
The patent employs the nesting principle by integrating the interconnection structure within the wafer substrate itself. The through-wafer vias are formed as hollow channels nested within the wafer material, and the conductive material is deposited directly onto the sidewalls of these nested channels. This nested configuration allows the interconnection pathways to be embedded within the device structure, eliminating external wiring and reducing packaging complexity while improving reliability.
3Area of stationary object
If through-wafer vias are formed with vertical sidewalls, then the area is minimized, but the shadowing effect prevents complete conductive coating coverage
Solution Approach 1:
The patent resolves this contradiction by introducing asymmetry in the via hole geometry. Instead of symmetric vertical sidewalls that create shadowing zones, the via holes are designed with asymmetric tapered sidewalls that angle inward. This asymmetric shape maintains a compact footprint while ensuring that all sidewall surfaces are directly exposed to the physical vapor deposition flux, eliminating shadowing effects and achieving complete conductive coating coverage.
Solution Approach 2:
The patent applies curvature principles by using sloping, curved sidewalls instead of straight vertical lines. The tapered geometry creates a smooth curved transition from the wider opening to the narrower bottom of the via hole. This curved geometry optimizes the surface area exposure to the deposition source while maintaining a compact via footprint, ensuring complete coating coverage without requiring excessive lateral space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in high-yield, reliable, and low-resistance through-wafer vias with improved mechanical support and thermal conductivity, reducing the risk of voids and enhancing the robustness and reliability of electronic devices.
Implementation Method 1
The through-wafer via hole comprises at least a first portion with a substantially vertical sidewall and a second portion forming a constriction in the through wafer via hole. The constriction comprises at least an upper sloping sidewall widening out towards the opening in the upper side
Implementation Method 2
The deposition of a conductive material on the sidewalls using a line-of-sight process such as PVD is a challenging operation
Implementation Method 3
allowing for improved conductive material coverage and adhesion
Data Source
AI summary
The present invention provides a wafer (3) comprising a through-wafer via (7) through the wafer (3) formed by a through-wafer via hole (9) and at least a first conductive coating (25). A substantially vertical sidewall (11) of the through-wafer via hole (9) except for a constriction (23) provides a reliable through-wafer via (7) occupying a small area on the wafer. The wafer (3) is preferably made of a semiconductor material, such as silicon, or a glass ceramic. A method for manufacturing such a wafer (3) is described.