Tapered Through Silicon Via Alignment in 3D Stacked Structures
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Solution Overview
Problem
Conventional through silicon via (TSV) stacked structures face challenges in accurate alignment and increased assembly height due to the need for precise alignment of straight conductive pins and extruded rings, leading to poor production yields and increased thickness in 3D chip stacking.
Innovation Solution
A tapered through silicon via structure with a wider recessed portion and a protruding narrower end is introduced, allowing for improved alignment and reduced thickness by fitting the narrower end of one via into the recessed portion of another, eliminating the need for additional protruding structures and enhancing joint stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If straight conductive pins are used for TSV connections, then electrical conductivity is achieved, but alignment accuracy deteriorates due to bending, deformation, or shifting during stacking processes
Solution Approach 1:
The conductive pin is segmented into two functional parts: an upper straight portion for electrical connection and a lower tapered portion for alignment. This segmentation allows each part to fulfill its specific function - the straight upper part maintains conductivity while the tapered lower part provides alignment tolerance
Solution Approach 2:
The conductive pin transitions from a symmetric cylindrical shape to an asymmetric tapered shape in the lower portion. This asymmetric tapered design creates a self-aligning mechanism where the pin can accommodate lateral deviations and still achieve proper alignment with the through-hole, resolving the contradiction between maintaining straightness for conductivity and allowing alignment tolerance
2Manufacturing precision
If extruded rings are used to connect stacked chips, then alignment is improved through nested ring fitting, but assembly height increases
Solution Approach 1:
The invention extracts and eliminates the separate extruded ring structure from the design. Instead of using additional rings for alignment, the alignment function is integrated directly into the conductive pin itself through the tapered portion, thereby removing the need for extra components that会增加 assembly height
Solution Approach 2:
The alignment function and electrical connection function are merged into a single integrated conductive pin structure. The tapered portion of the pin performs both alignment and conductivity functions simultaneously, eliminating the need for separate alignment rings and reducing overall assembly height
3Manufacturing precision
If additional protruding structures are used for alignment, then alignment accuracy is improved, but device complexity and assembly height increase
Solution Approach 1:
The conductive pin is designed as a universal component that performs multiple functions: electrical connection through its conductive material and alignment through its tapered geometry. This multi-functionality eliminates the need for separate alignment structures, reducing device complexity while maintaining alignment accuracy
Data Source
AI summary
A method of manufacturing through silicon via stacked structures. A plurality of substrates is provided. At least one tapered hole is formed on one surface of each substrate. Each tapered hole is filled up with a tapered through silicon via. A recessed portion is formed on the wider end of each tapered through silicon via. A part of the substrate is removed until the narrower end of each tapered through silicon via protrudes from the other surface of the substrate. The substrates is stacked one after another by fitting and jointing the narrower end of each tapered through silicon via on one substrate into a corresponding recessed portion of the tapered through silicon via of another substrate.