Tapered TSV via Ion Incidence Angle Optimization

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Solution Overview

Problem

The integration of semiconductor substrates using through-silicon via (TSV) technology faces challenges in stabilizing metal electrodes due to the high aspect ratio of TSVs, making it difficult to embed metals within the substrate holes effectively.

Innovation Solution

The semiconductor device employs a tapered shape for the silicon oxide film at the bottom of the through hole, allowing for a stable formation of barrier and seed metal layers by optimizing the ion incidence angle between 0° and 75°, particularly between 30° and 60°, which enhances the efficiency of reverse sputtering and metal layer coverage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a TSV with high aspect ratio is used for substrate integration, then higher performance semiconductor device is achieved, but it becomes difficult to embed metal into the hole and stabilize the through electrode

Engineering Contradiction:
Improvestability of through electrodeVSAvoiddifficulty to embed metal
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent changes the geometric parameters of the TSV by forming a tapered inner wall shape with a specific angle (30-60 degrees from vertical). This parameter change in the hole geometry enables better metal layer formation and adhesion, resolving the contradiction between achieving high-performance TSV integration and maintaining ease of metal embedding

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces asymmetry by creating a non-uniform TSV cross-section with a tapered shape rather than a cylindrical form. The asymmetric angle of the inner wall (30-60 degrees) provides improved surface area and adhesion characteristics for metal layers, making metal embedding feasible while maintaining the through-electrode function

Inventive Principle:
Principle #4Asymmetry

2Manufacturing precision

If metal layers are formed in high aspect ratio TSVs, then through electrode stability is required, but pinholes and incomplete coverage occur due to difficult metal embedding

Engineering Contradiction:
Improveuniformity of metal layer coverageVSAvoidpresence of pinholes
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

By changing the TSV inner wall angle parameter to 30-60 degrees from vertical, the patent creates optimal conditions for conformal metal layer deposition. This parameter adjustment ensures uniform metal coverage and eliminates pinhole formation, simultaneously improving manufacturing precision and reliability

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables more stable and uniform formation of metal layers within the TSVs, preventing pinholes and ensuring complete coverage, thereby improving the overall stability and performance of the semiconductor device.

Implementation Method 1

optimizing the ion incidence angle between 0° and 75°, particularly between 30° and 60°, which enhances the efficiency of reverse sputtering and metal layer coverage

Methodology Applied
Scientific EffectReverse sputtering: Sputtering

Data Source

PatentUS10269748B2Semiconductor device and manufacturing method of semiconductor device
Publication Date: 2019.04.23 KIOXIA CORP
  • US10269748B2 patent drawing
  • US10269748B2 patent drawing
  • US10269748B2 patent drawing

AI summary

A semiconductor device includes a semiconductor substrate provided with a through hole that extends therethrough from a first surface to a second surface on a side opposite to the first surface, a device layer provided at the first surface of the semiconductor substrate which includes an electrode, an insulating layer that covers the device layer, a first through electrode that extends through the insulating layer, an insulating layer that extends from the second surface of the semiconductor substrate to a bottom surface of the through hole through an inner surface of the through hole of the semiconductor substrate, and in which the portion thereof in contact with the bottom surface has a tapered shape, and a second through electrode electrically connected to the electrode in the device layer that is exposed to the bottom surface of the through hole.