Tapered Through-Silicon Via Structure for Void-Free Plating
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Solution Overview
Problem
Conventional through-silicon via (TSV) formation processes suffer from poor sidewall coverage of diffusion barrier layers and high likelihood of voids due to deep and narrow openings, leading to reduced throughput and adverse effects from undercuts during copper plating.
Innovation Solution
The formation of tapered TSVs with a hard mask region and shallow trench isolation (STI) structure, where the etching process is adjusted to create a tapered profile with reduced undercuts, and a polysilicon plate is used as an etch stop layer to enhance sidewall coverage and uniformity of the diffusion barrier layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If openings are made deep and narrow to achieve TSV formation, then through-silicon via connection is achieved, but sidewall coverage of diffusion barrier layer deteriorates and void formation increases
Solution Approach 1:
The patent applies asymmetry by creating a tapered opening profile where the upper portion is wider than the lower portion. This asymmetric geometry allows the opening to be deep enough for TSV connection while providing sufficient lateral space at the top for adequate diffusion barrier layer coverage, thereby resolving the contradiction between achieving deep via connection and maintaining uniform sidewall coverage
Solution Approach 2:
The patent changes the geometric parameters of the opening by controlling the etching process to create a tapered profile. By adjusting the etching conditions to produce a specific taper angle, the opening transitions from a uniform cylindrical shape to a tapered shape, which fundamentally changes the surface area available for barrier layer deposition and improves coverage uniformity
2Shape
If etching recipe is adjusted to increase lateral etching for tapered profile, then tapered TSV profile is achieved, but severe undercuts are formed
Solution Approach 1:
The patent applies local quality by using a hard mask layer selectively positioned at specific locations (such as the bottom or sides of the opening) to control etching behavior in different regions. This localized masking allows the upper portion to etch laterally forming the desired taper, while the lower portion maintains vertical walls to prevent severe undercuts
Solution Approach 2:
The hard mask layer serves as an intermediary element that mediates between the etching process and the silicon substrate. It controls the etching rate and direction locally, enabling the formation of a tapered profile in the upper region while preventing excessive lateral etching and undercut formation in the lower region
3Reliability
If plating current is reduced to avoid voids in TSVs, then void formation is reduced, but manufacturing throughput decreases
Solution Approach 1:
The patent applies preliminary action by pre-forming the tapered opening profile and applying the diffusion barrier layer before the copper plating process. This preliminary preparation creates optimal conditions for subsequent plating, allowing higher plating currents to be used without causing void formation, thereby maintaining both quality and throughput
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved sidewall coverage of the diffusion barrier layer, reduced undercuts, and increased plating current, leading to void-free TSVs with enhanced manufacturing efficiency.
Implementation Method 1
Silicon substrate 2 is then etched through opening 10, forming opening 12
Implementation Method 2
Copper (not shown) is then filled by plating to form a through-silicon via
Data Source
AI summary
An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV.