Tapered Under-Bump Terminal Structure for Compact Package Reliability
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving enhanced reliability and durability while maintaining a compact size, with existing technologies struggling to optimize the under-bump pattern and redistribution patterns for efficient electrical connectivity and structural integrity.
Innovation Solution
The semiconductor package incorporates a redistribution substrate with an under-bump pattern and specific dielectric layers and redistribution patterns, featuring a tapered shape and angled sidewalls, which allows for increased thickness and width variations to enhance connectivity and structural reliability, and skips the formation and removal of resist patterns to simplify fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the under-bump pattern thickness is increased to enhance reliability and durability, then the structural integrity improves, but the device size increases
Solution Approach 1:
The under-bump pattern is designed with asymmetric thickness distribution, being thicker at the bottom surface than at the top surface. This asymmetric configuration provides enhanced structural support and reliability at the base while reducing the overall height and volume of the device package.
Solution Approach 2:
The thickness parameter of the under-bump pattern is varied through its height, creating a tapered profile. This parameter change allows optimization of both mechanical strength (through increased bottom thickness) and compact size (through reduced top thickness), resolving the contradiction between reliability and device volume.
2Reliability
If the under-bump pattern width is increased at the top surface to improve electrical connectivity, then the connectivity improves, but the overall structure becomes less compact
Solution Approach 1:
The under-bump pattern exhibits asymmetric width variation, with the top surface width being greater than the bottom surface width. This asymmetric design ensures adequate electrical connectivity area at the top where it interfaces with the bump, while the narrower base maintains a compact overall structure.
Solution Approach 2:
The width parameter of the under-bump pattern changes through its height, creating a tapered geometry. This parameter variation allows the structure to provide sufficient connectivity area at the top interface while maintaining a compact footprint through the narrower bottom portion.
3Stability of the object's composition
If the sidewall angle is adjusted to optimize structural stability, then the structural integrity improves, but the manufacturing complexity increases
Solution Approach 1:
The sidewall of the under-bump pattern is designed with a specific asymmetric angle range (105° to 135°) rather than a vertical or highly tapered profile. This moderate asymmetric angle provides good structural stability while remaining compatible with standard semiconductor fabrication processes.
Solution Approach 2:
The sidewall angle parameter is optimized within a specific range (105° to 135°) to achieve the best balance between structural stability and manufacturability. This parameter optimization ensures the tapered structure is stable enough for reliable operation while being feasible to manufacture using conventional processes.
4Reliability
If the redistribution pattern thickness is increased to improve current carrying capacity, then the electrical performance improves, but the device height increases
Solution Approach 1:
The thickness parameter of the redistribution pattern is optimized to provide sufficient current carrying capacity while controlling the overall device height. The pattern thickness is increased only where necessary for electrical performance rather than uniformly throughout, maintaining a compact vertical profile.
Data Source
AI summary
Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.


