Tapered VA Structure for MTJ Alignment and Sputter Control
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Solution Overview
Problem
Traditional spin torque transfer magnetoresistive random access memory (STT-MRAM) faces cell size limitations due to drive transistor requirements and high write current and voltage needs, and scalability issues with traditional charge-based memory technologies, making it challenging to integrate effectively into high-performance logic chips.
Innovation Solution
The integration of spin torque transfer magnetic random access memory (STT-MRAM) arrays into logic processors using a magnetic tunnel junction (MTJ)-first approach, employing a tapered VA structure formed by damascene patterning to reduce alignment issues and sputter redeposition, which allows for tighter pitches and lower metal-to-dielectric ratios, minimizing shorts and voids in the MTJ devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If vertical sidewall VA structure is used, then alignment precision is improved, but sputter redeposition increases causing shorts and voids
Solution Approach 1:
The patent applies asymmetry by transitioning from a symmetric vertical sidewall VA structure to an asymmetric tapered VA structure. The tapered structure has a top opening width that is larger than the bottom width, creating an asymmetric profile that reduces sputter redeposition onto the MTJ pillar while maintaining alignment precision through the top opening geometry.
Solution Approach 2:
The patent applies curvature principles by using tapered sidewalls instead of straight vertical lines. The angled sidewalls create a curved transition from the top opening to the bottom, which redirects sputtered material away from the MTJ pillar and reduces redeposition-related defects.
2Area of moving object
If tighter pitches are used to increase density, then area is reduced, but alignment tolerance decreases
Solution Approach 1:
The asymmetric tapered structure provides a larger top opening relative to the bottom width, which increases the effective alignment target area. This allows tighter pitches to be used while maintaining adequate alignment tolerance, as the larger top opening is more forgiving of alignment variations during fabrication.
Solution Approach 2:
The patent changes the geometric parameters of the VA structure by introducing a taper angle and varying the width from top to bottom. This parameter change allows the structure to maintain functionality at tighter pitches while providing increased alignment tolerance through the modified geometry.
3Reliability
If conventional MTJ structures are used, then device functionality is achieved, but write current and voltage requirements are high
Solution Approach 1:
The patent changes the geometric parameters of the VA structure (taper angle, top opening width, bottom width) to optimize the device performance. These parameter changes lead to reduced sputter redeposition, which improves the quality of the MTJ structure and enables lower write current and voltage requirements while maintaining reliable device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more efficient integration of STT-MRAM arrays with improved alignment tolerance and reduced sputter redeposition, enhancing the scalability and reliability of MTJ devices, particularly at tighter pitches, by reducing the risk of shorts and voids, thus addressing the limitations of traditional STT-MRAM and charge-based memory technologies.
Implementation Method 1
The primary patterning method for the MTJ devices is physical sputtering (a nonselective etch method) so the underlying material layers are vulnerable to being sputter etched once the stack has been patterned.
Data Source
AI summary
A bottom electrode structure for MRAM or MTJ-based memory cells comprises a taper so that the bottom CD is smaller than the top CD. A process of making a bottom electrode contact structure comprises etching a dielectric layer using a plasma chemistry with an increased degree of polymerization. We obtain a product made by this process.