Tapered Via Connections in Stacked Semiconductor Packages
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high integration and structural stability, particularly in package-in-package (PIP) and package-on-package (POP) configurations, which affect their performance and reliability.
Innovation Solution
A semiconductor package design featuring multiple chips stacked with pillars and vias of varying dimensions and surface roughness, including a package substrate, first and second chips, and pillars and vias with decreasing widths, to enhance electrical connectivity and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chips are stacked in PIP or POP configuration to improve integration, then the integration level increases, but structural stability deteriorates
Solution Approach 1:
The connection structure is divided into multiple segments: pillars extending from upper chips, vias connecting pillars to lower chips, and multiple intermediate connection layers. This segmentation distributes mechanical stress across multiple interfaces rather than concentrating it at single bonding points, thereby maintaining structural stability while enabling high integration through multi-chip stacking.
Solution Approach 2:
The connection structure employs composite construction combining different materials and geometries: conductive pillars (likely metal), dielectric vias, and adhesive layers. This composite approach allows each material to contribute its optimal properties—electrical conductivity, mechanical strength, and bonding adhesion—creating a robust multi-chip assembly that maintains stability at high integration levels.
2Speed
If via width is reduced to improve signal transmission efficiency, then electrical connectivity improves, but manufacturing precision requirements increase
Solution Approach 1:
The via structure exhibits local quality variations: vias closer to the package substrate have larger widths for robust electrical connection and manufacturing tolerance, while vias extending toward upper chips have progressively smaller widths to optimize signal transmission. This gradient approach allows each via section to be optimized for its specific functional requirements while maintaining manufacturability.
Solution Approach 2:
The via width varies along the vertical dimension (distance from package substrate), creating a tapered or conical geometry rather than a uniform cylindrical shape. This dimensional variation allows the via to simultaneously achieve large cross-sectional area at the base for easy manufacturing and alignment, while maintaining small cross-section at the top for optimized signal transmission characteristics.
3Strength
If via surface roughness is increased to improve adhesion, then bonding strength improves, but manufacturing complexity increases
Solution Approach 1:
Different via sections have different surface roughness characteristics: the lower portions of via (closer to package substrate) have rougher surfaces to maximize adhesion strength at the critical bonding interface, while upper portions have smoother surfaces. This localized differentiation achieves optimal bonding where needed without unnecessarily complicating the entire via fabrication process.
Data Source
AI summary
A semiconductor package includes a package substrate, a first chip arranged to be spaced apart from the package substrate in a first direction perpendicular to the package substrate, a second chip disposed closer to the package substrate than the first chip and spaced apart from the package substrate, a first pillar extending along the first direction from the first chip toward the package substrate, a first via disposed between the first pillar and the package substrate, a second pillar extending along the first direction from the second chip toward the package substrate, and a second via disposed between the second pillar and the package substrate, and the first via and the second via have a width that decreases with distance away from the package substrate.