Tapered Via Holes for Void-Free Semiconductor Stacking
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Solution Overview
Problem
The increasing demand for high-integration semiconductor chips leads to elevated manufacturing costs, making it difficult to enhance individual chip capacity, which can be addressed by stacking semiconductor chips in modules connected via electrodes.
Innovation Solution
A semiconductor chip design featuring via holes with a tapered shape and corresponding electrodes that extend through the substrate, allowing for efficient stacking and connection of chips, including a Bosch process for forming the via holes and passivation layers to prevent voids and reduce electric resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via holes are formed using conventional methods, then manufacturing process is simple, but voids form in the via electrodes increasing electric resistance
Solution Approach 1:
The patent applies parameter changes by transitioning from a conventional cylindrical via hole shape to a tapered via hole shape with a wider opening at the top and narrower bottom. This geometric parameter modification allows via electrodes to be filled more effectively from the top, preventing void formation while maintaining manufacturing feasibility through standard etching processes that can produce tapered profiles.
Solution Approach 2:
The patent utilizes curvature principles by creating a tapered via hole profile with smooth curved transitions rather than sharp angles. The tapered shape with rounded contours facilitates uniform material deposition during via electrode formation, eliminating voids while the curved geometry maintains stress distribution and structural integrity during the stacking process.
2Quantity of substance
If individual semiconductor chip capacity is increased, then chip performance improves, but manufacturing cost increases significantly
Solution Approach 1:
The patent applies segmentation by dividing the high-capacity storage function across multiple individual semiconductor chips that are stacked vertically. Instead of attempting to increase the capacity of a single chip (which would be costly), the system segments the total capacity requirement into several smaller-capacity chips connected through the tapered via holes, achieving high overall capacity at lower individual chip costs.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement of chips to a three-dimensional vertical stacking configuration. By utilizing the vertical dimension and creating stacked modules connected through tapered via holes, the system achieves increased total capacity without requiring larger individual chip areas, thereby avoiding the exponential cost increase associated with scaling individual chip capacity.
3Quantity of substance
If multiple semiconductor chips are stacked to increase capacity, then overall chip capacity increases, but connection reliability between chips decreases
Solution Approach 1:
The patent applies parameter changes by modifying the via hole geometry from cylindrical to tapered shape. This geometric transformation ensures that via electrodes can be properly filled from the top opening, preventing void formation that would compromise electrical connectivity. The tapered profile with wider top and narrower bottom creates optimal conditions for electrode deposition, maintaining reliable electrical connections across multiple stacked chips.
Solution Approach 2:
The patent converts the potential harm of void formation in via electrodes into a benefit by using the tapered shape to prevent voids entirely. The wider opening at the top of the tapered via hole allows deposition materials to flow in and fill the structure completely, transforming what would be a defect-prone cylindrical geometry into a void-free configuration that enhances connection reliability in the stacked module.
Data Source
AI summary
A semiconductor chip, a method of fabricating the same, and a stack module and a memory card including the semiconductor chip include a first surface and a second surface facing the first surface is provided. At least one via hole including a first portion extending in a direction from the first surface of the substrate to the second surface of the substrate and a second portion that is connected to the first portion and has a tapered shape. At least one via electrode filling the at least one via hole is provided.