Tapered Void Memory Cell for Low Reset Current
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Solution Overview
Problem
Manufacturing high-density memory devices with small dimensions and low reset currents is challenging due to variations in process specifications needed for large-scale memory devices, particularly in reducing the magnitude of the reset current for phase change materials in integrated circuits.
Innovation Solution
A memory cell device structure is created with a first electrode and a separation layer, featuring a hole with downwardly and inwardly tapering void regions, where a memory material is deposited in electrical contact with the electrode, and a second electrode is formed to concentrate energy for changing electrical property states, using high-density plasma chemical vapor deposition (HDP CVD) to facilitate the formation of small phase change gates or bridges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the size of the phase change material element and contact area are reduced to lower reset current, then the reset current magnitude is reduced, but manufacturing precision and process control become more difficult
Solution Approach 1:
The patent segments the memory cell structure into distinct functional regions: a separation layer with a hole, a phase change material element within the hole, and electrode contact areas. This segmentation allows independent optimization of each component - the hole provides geometric confinement for low reset current while the separation layer and electrode design address manufacturing variability. The structured division enables precise control of current density distribution without requiring ultra-precise fabrication of the entire cell.
Solution Approach 2:
The patent applies local quality by creating a tapered or conical void region within the hole, where the cross-sectional area varies along the depth. This geometric variation concentrates current density specifically at the phase change material-electrode interface where it is most needed for low reset current, while the broader upper region provides manufacturing tolerance. The local geometric modification optimizes electrical properties without requiring uniform precision throughout the entire structure.
2Productivity
If small pores are used to reduce reset current, then device density is improved, but variations in process specifications increase
Solution Approach 1:
The patent transitions from two-dimensional planar contacts to three-dimensional vertical structures with holes and void regions. The hole extends through the separation layer with controlled depth and diameter, creating a vertical current path that concentrates energy through the phase change material. This dimensional change allows density improvement through vertical stacking while the hole geometry provides inherent process tolerance, as the tapered void region can accommodate variations in deposition and etching processes.
Solution Approach 2:
The patent utilizes parameter changes by controlling the hole dimensions (diameter, depth, aspect ratio) and the phase change material layer thickness within the hole. By optimizing these geometric parameters, the design achieves high device density while maintaining robustness against process variations. The specific parameter set - hole diameter of 50-200 nm, depth of 50-500 nm, and phase change material thickness of 5-50 nm - provides a window of tolerance that balances density with manufacturing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the reduction of reset current magnitude by confining current flow through a small volume of memory material, enabling the creation of small-scale memory devices with improved manufacturing precision and scalability, eliminating the need for chemical mechanical polishing.
Implementation Method 1
A second material and is on the side wall with the second material defining a void. The void has a downwardly and inwardly tapering void region below the plane of the upper surface.
Implementation Method 2
The second material may comprise a high density plasma-deposited material.
Data Source
AI summary
A memory cell device, having a memory material switchable between electrical property states by the application of energy, comprises an electrode, a separation layer against an electrode surface, a hole in the separation layer, a second material in the hole defining a void having a downwardly and inwardly tapering void region. A memory material is in the void region in electrical contact with the electrode surface. A second electrode is in electrical contact with the memory material. Energy passing between the first and second electrodes is concentrated within the memory material so to facilitate changing an electrical property state of the memory material. The memory material may comprise a phase change material. The second material may comprise a high density plasma-deposited material. A method for making a memory cell device is also discussed.