Tapped Delay Line Timing for High-Resolution Frequency Measurement
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Solution Overview
Problem
Conventional reciprocal counters face limitations in resolution due to dependence on timer clock speed, leading to inaccuracies and increased power consumption when attempting to improve resolution by increasing timer clock speed, and existing solutions using delay lines still incur power and cost increases.
Innovation Solution
The use of tapped delay lines with multiple stages and fractional correction time values to improve timestamp accuracy for signal timing edges, allowing for higher resolution without increasing timer clock speed, achieved through a combination of delay line taps and timer counter capture registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If timer clock speed is increased to improve resolution, then measurement precision improves, but power consumption increases
Solution Approach 1:
The timer clock period is segmented into multiple phases, with each phase capturing the state of a different delay line tap. This allows the system to achieve fine resolution (equivalent to a much faster clock) by sampling at multiple points during a single clock cycle, thereby maintaining low power consumption while improving measurement precision.
Solution Approach 2:
Delay line taps serve as intermediaries that capture signal states at different time points within a clock cycle. These taps provide fractional timing information without requiring a faster clock, enabling high-resolution measurement while keeping the timer clock speed (and thus power consumption) low.
2Measurement precision
If timer clock speed is increased to improve resolution, then measurement precision improves, but system cost increases
Solution Approach 1:
The system segments the timing measurement process into multiple phases, each handling a portion of the timing information. This allows the use of a slower, less expensive timer clock while achieving the same effective resolution that would require a much faster (and more expensive) clock in a conventional system.
Solution Approach 2:
The delay line creates temporal copies of the signal at different time points. By capturing these copies at discrete phases, the system reconstructs fine timing information without needing a high-speed clock, thereby reducing system cost while maintaining measurement precision.
3Use of energy by moving object
If delay lines are used to improve resolution without increasing timer clock speed, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent merges the delay line functionality with the timer counter operation. The delay line taps are integrated into the existing timer infrastructure, sharing clock signals and control logic. This consolidation reduces overall device complexity compared to having separate delay line and timing measurement systems.
Solution Approach 2:
The delay line serves multiple functions: it provides timing resolution enhancement, generates phase-shifted signals for multi-phase sampling, and works with the existing timer counter to produce high-resolution frequency measurements. This multi-functionality reduces the need for additional dedicated circuits, thereby managing device complexity.
Data Source
AI summary
Methods for determining timestamps for signal timing edges for use in, e.g., a reciprocal counter for determining the frequency of a signal is disclosed, comprising the steps of inputting the signal into a tapped delay line, producing a plurality of delay line tap signals at the output of each of the delay line taps. In one embodiment, after detecting the signal timing edge and determining an initial time value corresponding to the timer clock cycle count at the signal timing edge or the next clock timing edge, the delay line tap signals are monitored to determine a fractional correction time value adjustment to be made to the initial value to account for the delay between the signal timing edge and the next clock timing edge to determine the timestamp. In another embodiment, after detecting the signal timing edge, the average of a plurality of delay line timer clock cycle counts corresponding to the timer clock cycle counts at the delay line tap signal timing edges is used to determine the timestamp.