Tapped Delay Circuit for Reliable Time-to-Digital State Capture
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Solution Overview
Problem
Existing time interval measurement circuits, such as those described in Patent Literature 1, face issues with acquiring accurate state information due to fluctuations in high-frequency counter values and ring oscillator oscillations, leading to potential errors in timing measurements.
Innovation Solution
A delay circuit with a state transition section and a transition-state acquisition section, including a tapped delay line, logical circuits, and a synchronous transition section, which transitions states based on a trigger signal and latches state information, allowing for accurate calculation of time digital values by weighting and accumulating state transition times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-frequency counter and ring oscillator operate independently to measure time intervals, then the measurement circuit can acquire coarse and fine values separately, but the likelihood of acquiring wrong state information increases due to fluctuations in count value and oscillation
Solution Approach 1:
The patent merges the high-frequency counter and ring oscillator into a unified state transition section where they operate synchronously rather than independently. The counter and oscillator share a common clock signal and update mechanism, ensuring that coarse and fine values are captured at the same moment in time. This eliminates the timing mismatch problem where independent operation could cause the counter and oscillator to report inconsistent states, thereby resolving the contradiction between measurement precision and reliability.
Solution Approach 2:
The patent implements feedback mechanisms where the state transition section continuously monitors and adjusts the operation of both the counter and oscillator based on captured time interval signals. The system uses feedback loops to synchronize the update timing of coarse and fine values, ensuring that both components reflect the same temporal moment. This feedback control prevents the acquisition of wrong state information while maintaining high measurement precision.
2Productivity
If the state transition section updates state information frequently, then the time digital value calculation can capture more state transitions, but the time required for state transition may become insufficient
Solution Approach 1:
The patent employs dynamic update timing where the state transition section adjusts its sampling rate based on the actual time interval being measured. For shorter time intervals, the system captures state transitions more frequently to maintain productivity, while for longer intervals, it allows sufficient time between updates. The state transition section dynamically adapts its operation speed to match the measured time interval, ensuring both high capture rate and adequate transition duration are achieved appropriately.
Solution Approach 2:
The system changes the operational parameters of the state transition section based on the measured time interval characteristics. When measuring short intervals, the system increases the update frequency and reduces the time between state captures. When measuring longer intervals, it decreases the update frequency to allow complete state transitions. This parameter adaptation resolves the contradiction by optimizing the balance between productivity and transition duration for different measurement scenarios.
Data Source
AI summary
A delay circuit includes a state transition section configured to start state transition based on a trigger signal and output state information indicating the internal state and a transition-state acquisition section configured to latch and hold the state information. The state transition section includes a tapped delay line in which a plurality of delay elements are coupled, a logical circuit configured to generate a third signal based on a first signal based on the trigger signal and a second signal, which is an output signal of the delay element, and a synchronous transition section configured to count an edge of the third signal. The state information is having an output signal of the synchronous transition section and an output signal of the tapped delay line. A humming distance of the state information before and after the state transition is 1. A time from when the internal state transitions from a first internal state to a second internal state until when the internal state transitions to the first internal state again is longer than an interval of a time for updating the state information held by the transition-state acquisition section.