Target-Aware Neural Network Channel Pruning for Embedded Inference

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Solution Overview

Problem

Machine learning methods, particularly neural networks, are computationally expensive and challenging to deploy on resource-constrained embedded systems without compromising accuracy or meeting performance requirements.

Innovation Solution

A target-aware pruning method that combines channel importance metrics and on-target profiling information to identify and remove less important channels, reducing the complexity of neural networks while maintaining inference performance and accuracy, applicable to various hardware devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If machine learning methods (neural networks) are used to improve accuracy and performance, then the model accuracy and inference performance are improved, but the computational complexity and resource requirements increase

Engineering Contradiction:
Improvemodel accuracyVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes less important channels from neural network layers based on importance metrics. This pruning approach eliminates redundant computational elements while preserving the essential functionality needed for accurate inference, thereby reducing computational complexity without significantly compromising model accuracy

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter configuration of the neural network by dynamically adjusting the number of active channels in each layer. By modifying the network architecture parameters based on importance analysis, the system achieves a balance between computational efficiency and accuracy requirements for embedded deployment

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If neural network complexity is reduced to meet resource constraints, then the device complexity is reduced, but the inference performance and accuracy may deteriorate

Engineering Contradiction:
Improvenetwork complexityVSAvoidinference performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies local quality by differentiating between important and unimportant channels within the network. Instead of uniformly reducing complexity across all layers, the method selectively prunes channels based on their local importance metrics, ensuring that critical functionality is preserved while removing redundant elements

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs feedback mechanisms by evaluating the impact of channel pruning on inference performance and using this information to iteratively refine the pruning process. Importance metrics are computed based on actual network behavior, and pruning decisions are adjusted based on performance feedback to maintain accuracy

Inventive Principle:
Principle #23Feedback

3Productivity

If channel pruning is applied to reduce computational complexity, then the productivity and execution speed are improved, but the model accuracy may be compromised

Engineering Contradiction:
Improveinference execution speedVSAvoidmodel accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent performs preliminary analysis to compute channel importance metrics before executing the pruning process. By pre-evaluating channel importance based on network activations and gradients, the system identifies which channels can be safely removed without impacting accuracy, enabling accurate inference at reduced computational cost

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3945470A1Methods and systems for reducing the complexity of a computational network
Publication Date: 2022.02.02 APTIV TECHNOLOGIES AG
  • EP3945470A1 patent drawingFigure 1
  • EP3945470A1 patent drawingFigure 2
  • EP3945470A1 patent drawing

AI summary

A computer implemented method for reducing the complexity of a computational network comprises the following steps carried out by computer hardware components: determining computational complexity of at least one portion of the computational network; determining an effect of a reduction of a complexity of the computational network on an output of the computational network; and determining how to reduce the complexity of the computational network based on the determined computational complexity and based on the effect.