Target-Chip Cache Selection for Shared Accelerator Prefetch

The patent applies local quality by making different caches have different functions based on their current workload status. The target chip dynamically identifies which cache is least busy and directs prefetch operations to that specific cache, rather than using a fixed cache allocation strategy. This allows the system to optimize accelerator sharing performance while minimizing interference with existing workloads by adapting cache usage to local conditions on the target chip.

The patent applies segmentation by dividing the cache resource into multiple independent caches that can be independently managed. The target chip monitors each cache's workload separately and selects the most appropriate cache for prefetch operations. This segmentation provides data placement flexibility while keeping the selection logic relatively simple - the system only needs to identify which cache is least busy rather than managing complex data placement across all caches simultaneously.

The patent applies inversion by reversing the traditional control model. Instead of the external processor controlling where data should be prefetched, the target chip autonomously determines the optimal cache location for prefetch operations. The external processor simply initiates prefetch requests, and the target chip's cache-activity monitoring logic independently decides which cache to use. This maintains high accelerator utilization while restoring control capability to the target chip.