Target Detection Network for Parasitic Extraction in IC Layouts
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Solution Overview
Problem
Existing methods for extracting parasitic parameters in digital integrated circuits are inefficient due to pattern matching errors and the laborious process of establishing pattern libraries, especially as process nodes advance and circuit scales increase, with previous approaches focusing on two-dimensional views of three-dimensional layouts.
Innovation Solution
A method utilizing a target detection network to simplify the establishment of a pattern library and conduct accurate pattern matching by generating image sets, training the network, and using it to predict parasitic capacitance values from layout images, incorporating loss function optimization and geometric structure classification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pattern matching method is used with manual pattern library establishment, then parasitic extraction can be performed for large-scale circuits, but the process is time-consuming and laborious with pattern matching errors
Solution Approach 1:
The system performs self-learning by automatically generating training data from layout files and refining the pattern library through iterative training cycles. The neural network learns parasitic patterns autonomously without manual intervention, improving both efficiency and accuracy simultaneously
Solution Approach 2:
The patent transforms the static pattern library into a dynamic learning system by changing parameters through training iterations. The network adjusts its internal parameters (weights and biases) based on loss function optimization, enabling adaptive improvement of matching accuracy while maintaining high extraction efficiency
2Ease of operation
If traditional two-dimensional cross-sectional view is used, then parasitic parameters can be extracted by dividing three-dimensional layouts, but the method accumulates errors and loses planar information
Solution Approach 1:
The patent introduces a new dimensional perspective by treating layout layers as images with spatial coordinates. Instead of dividing 3D layouts into 2D cross-sections, the method processes each layer as a 2D image plane, preserving planar geometric information while enabling direct image-based pattern recognition that maintains extraction accuracy
Data Source
AI summary
A method for parasitic extraction based on a target detection network. The method includes the following steps: establishing a parasitic capacitance pattern library; creating a dataset that conforms to layout interconnection features; training the target detection network by using a self-established dataset and optimizing the network by modifying loss functions; predicting layout images by a trained network, conducting a subsequent processing on predicted results of the network and obtaining values for parasitic parameters. This provides a simple and optional solution for establishing a parasitic parameters pattern library and conducting a pattern matching in the digital integrated circuit.