Semiconductor Target Pattern Layout for Automated Capacitance Inspection

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Solution Overview

Problem

Current inspection methods for semiconductor structures after dual patterning are labor-intensive and cannot be automated, making it challenging to inspect large quantities efficiently.

Innovation Solution

A semiconductor structure design that includes multiple pairs of target patterns with conductive lines electrically connected to specific patterns, allowing for electrical inspection to detect structural homogeneity through capacitance values, thereby automating the inspection process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Extent of automation

If manual visual inspection by random testing is used, then inspection can be performed, but the method is labor-intensive and cannot be automated

Engineering Contradiction:
Improveinspection automationVSAvoidinspection throughput
Core Design Contradiction:
Extent of automationVSProductivity

Solution Approach 1:

The patent replaces manual visual inspection with an electrical measurement system that uses conductive lines and capacitance measurement to automatically detect pattern defects. This substitution of mechanical/manual inspection with an electrical measurement system enables automation and high-throughput inspection without labor-intensive manual testing.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If electrical inspection with conductive lines is used, then automation and large quantity inspection are enabled, but the device structure becomes more complex

Engineering Contradiction:
Improveinspection throughputVSAvoidstructure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The conductive lines serve multiple functions: they act as electrical connection paths for power supply and signal transmission, and simultaneously serve as measurement electrodes for capacitance-based defect detection. This multi-functionality reduces the need for separate inspection structures, thereby limiting the increase in device complexity while enabling automated high-throughput inspection.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Quantity of substance

If critical dimensions are reduced, then integration of semiconductor components is increased, but photolithography process becomes more difficult

Engineering Contradiction:
Improvecomponent integrationVSAvoidphotolithography process
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent introduces an intermediary measurement mechanism (capacitance measurement through conductive lines) that indirectly detects pattern defects without requiring direct optical visualization. This intermediary approach enables inspection of densely integrated structures where direct photolithography observation becomes difficult, allowing continued scaling of component integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution enables automated electrical inspection of semiconductor structures, improving yield and throughput by ensuring structural homogeneity and stability in semiconductor processes.

Implementation Method 1

the structural homogeneity of the core pattern can be detected by the core capacitance value and/or gap capacitance value obtained from electrical inspection

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12288689B2Semiconductor structure
Publication Date: 2025.04.29 WINBOND ELECTRONICS CORP
  • US12288689B2 patent drawing
  • US12288689B2 patent drawing
  • US12288689B2 patent drawing

AI summary

Provided is a semiconductor structure including multiple pairs of target patterns, a first conductive line, and a second conductive line. Each of the pairs of target patterns includes a top pattern and a bottom pattern. The first conductive line is disposed on a first side of the pairs of target patterns. The first conductive line is electrically connected to a top pattern of a (aN+1)th pair of target patterns in the pairs of target patterns, a is a fixed integer greater than or equal to 2, and N is an integer greater than or equal to 0. The second conductive line is disposed on a second side of the pairs of target patterns opposite to the first side. The second conductive line is electrically connected to a bottom pattern of the (aN+1)th pair of target patterns in the pairs of target patterns.