Target Port Multicast Transactions for Memory Bandwidth Efficiency
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Solution Overview
Problem
Integrated circuit devices face inefficiencies in data transfer due to the lack of multicast transaction capabilities in their internal communication fabrics, particularly in standardized bus protocols like AXI, which limits the ability to efficiently load data into multiple accelerators simultaneously, leading to suboptimal utilization of computational arrays in neural networks.
Innovation Solution
Implementing a communication fabric that enables multicast transactions and staggered data distribution across memory banks, using a master port with multicast address ranges to generate multiple transactions for multiple targets and a target port that distributes data across memory banks, allowing data to be read once and written to multiple locations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standardized bus protocol is used for communication fabric, then implementation is simplified and interface circuits can be reused, but multicast transaction capability is lost and data cannot be efficiently distributed to multiple targets
Solution Approach 1:
The target port is segmented into multiple independent target interfaces (first target interface, second target interface, etc.), each capable of receiving transactions independently. This allows a single master port to efficiently distribute data to multiple targets through parallel interfaces while maintaining the simplicity of standardized bus protocols for each individual interface.
2Quantity of substance
If separate write transactions are generated for each location to move the same data, then data can be written to multiple locations, but memory bandwidth is wasted and transfer efficiency is reduced
Solution Approach 1:
Multiple separate write transactions are merged into a single multicast transaction. The master port generates one transaction that is simultaneously received by multiple target interfaces, which then distribute the data to multiple memory locations in parallel. This combining approach reduces memory bandwidth consumption while achieving the same data distribution goal.
Solution Approach 2:
The transaction is copied and distributed to multiple target interfaces simultaneously. Instead of sending the same data through separate transaction sequences, the transaction itself is replicated across multiple targets, enabling efficient one-to-many data distribution without proportionally increasing bandwidth usage.
3Reliability
If data is loaded sequentially into multiple accelerators, then each accelerator receives complete data, but computational arrays are underutilized and processing time increases
Solution Approach 1:
Data is preliminarily distributed to multiple accelerators simultaneously through multicast transactions before computation begins. This preliminary parallel distribution ensures all accelerators have the required data ready, enabling immediate utilization of computational arrays without sequential waiting, thus improving overall productivity while maintaining data completeness.
Data Source
AI summary
Provided are integrated circuit devices and methods for operating integrated circuit devices. In various examples, the integrated circuit device can include a target port operable to receive transactions from a master port. The target port can be configured with a multicast address range that is associated with a plurality of indices corresponding to memory banks of the device. When the target port receives a write transaction that has an address that is within the multicast address range, the target port can determine an index from the plurality of indices, and can use the index to determine a second address, which combines the index and the offset value with the address. The target port can then use the second address to write the data to the memory.