Target Voltage Circuit Using Parallel Bus for Fast APT Switching

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Solution Overview

Problem

Conventional power management circuits in 5G-NR wireless communication devices face challenges in adapting average power tracking (APT) voltage quickly enough to maintain linearity and efficiency of Wi-Fi power amplifiers, as the temporal limit for voltage adaptation is often as short as 0.5 microseconds, and existing serial bus transmission methods are too slow to achieve this within the required timeframe.

Innovation Solution

A target voltage circuit that receives digital target voltage words via a parallel bus, allowing for faster processing and generation of time-variant target voltages, thereby enabling the power management circuit to switch between voltage levels within the defined temporal limit by using a front-end circuit and processing circuit that determines and generates target voltages based on the received digital data signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If serial bus transmission is used to transmit target voltage data, then device complexity is reduced, but transmission speed is too slow to meet the 0.5 microsecond temporal limit

Engineering Contradiction:
Improvetransmission speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent transitions from serial bus transmission (one-dimensional time-based data transfer) to parallel bus transmission (multi-dimensional simultaneous data transfer). By receiving multiple data signals simultaneously through parallel bus lines, the target voltage word is transmitted all at once rather than bit-by-bit sequentially, achieving the required 0.5 microsecond response time while maintaining reasonable device complexity through the use of standard parallel bus interfaces.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of time

If parallel bus is used to receive digital target voltage word, then transmission delay is reduced, but device complexity increases

Engineering Contradiction:
Improvetransmission delayVSAvoiddevice complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The power management circuit performs preliminary action by receiving the complete target voltage word through parallel bus before any voltage switching is required. This allows the circuit to process and prepare the voltage transition in advance, ensuring that the actual voltage switching can be executed within the 0.5 microsecond temporal limit without rushing or timing conflicts.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If voltage switching is performed within 0.5 microsecond temporal limit, then power amplifier efficiency is maintained, but circuit complexity increases

Engineering Contradiction:
Improvevoltage switching speedVSAvoidcircuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the voltage switching function into distinct operational phases: receiving the target voltage word through parallel bus, processing the received data to determine the voltage transition, and executing the switching operation. This segmentation allows each sub-function to be optimized independently, achieving the 0.5 microsecond overall response time without requiring every component to be excessively complex.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11349468B2Target voltage circuit for fast voltage switching
Publication Date: 2022.05.31 QORVO US INC
  • US11349468B2 patent drawing
  • US11349468B2 patent drawing
  • US11349468B2 patent drawing

AI summary

A target voltage circuit for fast voltage switching is provided. The target voltage circuit is configured to generate a time-variant target voltage(s) to thereby cause a power management circuit to generate a time-variant voltage(s) for a power amplifier circuit. In embodiments disclosed herein, the target voltage circuit receives a number of data signals (e.g., from a transceiver circuit via a parallel bus) that collectively represent a digital target voltage word and maps the digital target voltage word to a target voltage(s). By receiving the digital target voltage word corresponding to the target voltage(s) via the parallel bus, as opposed to directly receiving the target voltage(s) via a serial bus, it is possible to reduce transmission delay. As a result, the power management circuit will be able to switch the time-variant voltage(s) from one voltage level to another based on the target voltage(s) within a defined temporal limit.