Targeted Power Grid Structure for IR-Drop Reduction

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Solution Overview

Problem

In integrated circuits, significant IR drops occur at high-current cells like clock buffer cells, affecting performance due to voltage loss across power grid conductive lines and vias, and increasing power grid density to mitigate this leads to design rule violations and performance issues.

Innovation Solution

Implementing localized low-resistance paths between IR-drop hotspots and power supply lines, which are electrically isolated from other cells, to reduce voltage loss without increasing power grid density across the entire circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If power grid density is increased to reduce IR-drop, then voltage loss is reduced, but design rule violations and performance issues occur

Engineering Contradiction:
ImproveIR-dropVSAvoidpower grid density
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating localized low-resistance paths only at specific locations where IR-drop hotspots are identified, rather than uniformly increasing power grid density across the entire circuit. This targeted approach reduces voltage loss at critical cells (such as clock buffer cells) while maintaining standard power grid density in other regions, thereby avoiding design rule violations and performance issues associated with excessive density.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The power grid is segmented into standard regions and targeted regions with low-resistance paths. The patent divides the power distribution network into regular power grid areas and specific localized areas requiring enhanced power delivery, allowing different density characteristics in different segments to optimize both overall circuit performance and local voltage stability.

Inventive Principle:
Principle #1Segmentation

2Loss of energy

If power grid density is increased to reduce IR-drop, then voltage loss is reduced, but area and power consumption increase

Engineering Contradiction:
ImproveIR-dropVSAvoidpower grid area
Core Design Contradiction:
Loss of energyVSArea of stationary object

Solution Approach 1:

Instead of increasing power grid density uniformly across the entire chip area, the patent implements low-resistance paths only in localized regions where IR-drop hotspots are detected. This approach reduces the total area occupied by power grid structures while effectively addressing voltage loss at critical locations, thereby improving power, performance, and area (PPA) metrics.

Inventive Principle:
Principle #3Local quality

3Loss of energy

If power grid density is increased to reduce IR-drop, then voltage loss is reduced, but manufacturing complexity increases

Engineering Contradiction:
ImproveIR-dropVSAvoidpower grid fabrication
Core Design Contradiction:
Loss of energyVSEase of manufacture

Solution Approach 1:

The patent simplifies manufacturing by implementing a selective approach where low-resistance paths are created only at identified hotspot locations using standard fabrication processes. This localized modification avoids the complexity of redesigning the entire power grid structure, maintaining ease of manufacture while effectively reducing IR-drop at critical cells through targeted conductor modifications.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces IR-drop at targeted cells, enhancing performance and utilization without increasing power grid density elsewhere, thus improving power, performance, and area (PPA) metrics in integrated circuits.

Implementation Method 1

a conductive path between a power supply line and an active layer in an integrated circuit device... reducing the IR-drop between the power supply line and the active layer

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20220328409A1Targeted power grid structure and method
Publication Date: 2022.10.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20220328409A1 patent drawing
  • US20220328409A1 patent drawing
  • US20220328409A1 patent drawing

AI summary

In some embodiments, a low-resistance path between an active cell and a power supply layer in an integrated circuit device includes at least one layer of a plurality of conductive lines commonly connected to at least one conductive line through a plurality of respective conductive pillars, the at least one conductive line being in the power supply layer or intervening the active cell and the power supply layer. In some embodiments, the integrated circuit device includes a conductive layer that includes the plurality of conductive lines and additional conductive portions, where the plurality of conductive lines are isolated from the additional conductive portions.