Task-Based Computing Checkpointing for Low-Latency Recovery

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Solution Overview

Problem

Computing systems handling real-time data processing face challenges in achieving recoverability, fault tolerance, and high availability while maintaining low latency, especially when dealing with multiple interacting data processing programs and continuous data streams.

Innovation Solution

The implementation of a task-based computing system with high-frequency checkpointing (10 ms to 100 ms) and pulsed ingestion algorithms, which divide data streams into pulses for processing, allowing for efficient recovery and maintaining low latency by storing checkpoints and escrowed output data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high-frequency checkpointing is implemented to improve recoverability and fault tolerance, then system reliability is improved, but processing latency increases

Engineering Contradiction:
Improvefault toleranceVSAvoidprocessing latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the checkpointing process into multiple independent components: input pulse separation, processing pulse generation, and output pulse separation. Each component operates independently with its own timing and control logic, allowing the system to perform checkpointing operations without blocking the main data processing flow. This segmentation enables fault tolerance through frequent checkpoints while maintaining low latency by preventing checkpoint operations from serializing the processing pipeline.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by pre-separating input pulses before processing and pre-generating processing pulses in advance. The system prepares checkpoint data structures and buffers ahead of time, so that when a checkpoint is needed, the data is already organized and ready for rapid serialization. This preliminary preparation eliminates the need for time-consuming data organization during actual checkpoint operations, thus improving reliability through frequent checkpoints without adding latency.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If checkpointing frequency is increased to reduce recovery time, then recoverability is improved, but system complexity increases

Engineering Contradiction:
ImproverecoverabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a universal pulse separation and processing mechanism that handles multiple functions through a single standardized interface. The same pulse separation logic is used for both input data and output data, and the processing pulse generator serves both checkpointing and normal processing needs. This multi-functionality reduces system complexity by eliminating redundant components while still supporting high-frequency checkpointing for improved recoverability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system implements self-service through automatic pulse separation and processing pulse generation without requiring external control logic. The checkpointing mechanism automatically identifies when checkpoints are needed, separates the relevant data pulses, generates processing pulses, and manages the checkpoint creation process autonomously. This self-service approach reduces complexity by eliminating the need for complex external coordination while enabling frequent checkpointing for better recoverability.

Inventive Principle:
Principle #25Self-service

3Reliability

If escrowed output data is maintained to ensure data integrity, then reliability is improved, but memory usage increases

Engineering Contradiction:
Improvedata integrityVSAvoidmemory usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent implements periodic action by maintaining escrowed output data only for the duration of a single processing pulse interval. Instead of continuously buffering all output data, the system periodically releases escrowed data once the corresponding input pulse has been successfully processed and checkpointed. This periodic release mechanism ensures data integrity by holding data temporarily when needed while minimizing memory usage by releasing buffers promptly, thus improving reliability without significantly increasing memory requirements.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP3614266B1Recoverable stream processing
Publication Date: 2022.03.09 AB INITIO TECHNOLOGY LLC
  • EP3614266B1 patent drawingFigure 1
  • EP3614266B1 patent drawingFigure 2A~2C
  • EP3614266B1 patent drawingFigure 3

AI summary

A computing system (100) includes nodes (152) executing data processing programs that each process at least one stream of data units. A data storage system (156, 157) stores shared data accessible by at least two of the programs. Processing at least one stream using a first data processing program includes: processing a first stream of data units that includes multiple subsets of contiguous data units; initiating termination of processing within the first data processing program, between processing a first subset of contiguous data units and processing a second subset of contiguous data units adjacent to the first subset of contiguous data units within the first stream of data units; durably storing at least some changes to the shared data caused by processing the first subset of contiguous data units after determining that the termination of processing within the first data processing program has completed; and resuming processing within the first data processing program.