Task Context Transfer for Accelerator Processing

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Solution Overview

Problem

Current task switching techniques in data processing devices are inefficient in transferring and restoring task context information, particularly during accelerator calls, leading to delays and suboptimal resource utilization.

Innovation Solution

The method involves transferring task context information in an out-of-order sequence to facilitate accelerator processing by providing necessary register values before saving other register values, and merging accelerator results with task context information during restoration, using an Application Binary Interface (ABI) protocol to determine the transfer order.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If task context information is transferred in a sequential in-order sequence, then the transfer process is simple to implement, but the accelerator processing is delayed due to waiting for all register values

Engineering Contradiction:
ImproveImplementation simplicityVSAvoidAccelerator processing delay
Core Design Contradiction:
Ease of manufactureVSLoss of time

Solution Approach 1:

The patent applies preliminary action by identifying and transferring accelerator input register values before other register values during the context switch process. The task switch circuit determines which registers contain input values for the accelerator and transfers these specific values in advance, allowing the accelerator to begin processing sooner while maintaining implementation feasibility through targeted pre-transfer of critical data.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If all register values are transferred to context storage before accelerator processing, then data integrity is maintained, but system performance is reduced due to idle time

Engineering Contradiction:
ImproveData integrityVSAvoidSystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the task context information into different categories: accelerator input values, other register values, and accelerator output values. The task switch circuit transfers these segments in different phases - input values first to enable immediate accelerator processing, then other register values, and finally merges accelerator output values with the restored context. This segmentation maintains data integrity while eliminating idle time and improving system performance.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If the processor waits for accelerator completion before resuming task, then task context restoration is straightforward, but processor utilization is reduced

Engineering Contradiction:
ImproveContext restoration complexityVSAvoidProcessor utilization
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent enables continuity of useful action by allowing the processor to resume executing the task immediately after transferring the necessary register values, without waiting for accelerator completion. The task switch circuit transfers register values containing accelerator input data, then the processor can continue execution while the accelerator operates independently. The accelerator output values are merged with the task context later, maintaining straightforward restoration while maximizing processor utilization.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS10031773B2Method to communicate task context information and device therefor
Publication Date: 2018.07.24 NXP USA INC
  • US10031773B2 patent drawing
  • US10031773B2 patent drawing
  • US10031773B2 patent drawing

AI summary

Task context information is transferred concurrently from a processor core to an accelerator and to a context memory. The accelerator performs an operation based on the task context information and the context memory saves the task context information. The order of transfer between the processor core is based upon a programmable indicator. During a context restore operation information is concurrently provided to data bus from both the accelerator and the processor core.