Task Distribution Circuit for Load Balancing in Multi-Unit Systems
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Solution Overview
Problem
Modern computing systems with multiple processing units face challenges in efficiently distributing processing tasks, leading to uneven workload distribution, out-of-order processing, and increased latency, particularly in handling network packets from different flows.
Innovation Solution
A control logic circuit selects appropriate task distribution techniques based on categories of processing tasks and the load status and capability of processing units, using methods like round robin, weighted round robin, and receive side scaling to ensure even distribution and reduce out-of-order processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processing units operate in parallel to improve throughput, then system throughput is improved, but workload distribution becomes uneven leading to some units being overloaded while others are underutilized
Solution Approach 1:
The patent implements dynamic workload distribution by continuously monitoring the load status of multiple processing units and adapting task allocation in real-time. The control logic circuit adjusts which processing unit handles which network flow based on current utilization, preventing both overload and underutilization. This dynamic approach resolves the contradiction by maintaining balanced workload distribution while preserving parallel processing capabilities for high throughput.
2Device complexity
If processing tasks are distributed randomly or using simple algorithms, then implementation complexity is reduced, but out-of-order processing occurs increasing latency
Solution Approach 1:
The patent introduces an intermediary control logic circuit that sits between the network interface and processing units. This intermediary monitors packet flow characteristics, identifies related packets from the same network flow, and ensures they are routed to the same processing unit in the correct order. This intermediary layer adds minimal complexity while eliminating out-of-order processing and associated latency.
3Ease of operation
If processing units are selected based on load status and task characteristics, then load balance is improved, but the complexity of selection logic increases
Solution Approach 1:
The patent changes the selection parameters from complex multi-dimensional analysis to simpler, more manageable parameters. The control logic circuit monitors basic load status indicators and packet flow characteristics, using these changed parameters to make selection decisions. This parameter transformation maintains effective load balancing while reducing selection mechanism complexity to implementable levels.
4Productivity
If network packets from the same flow are processed by different processing units, then parallel processing efficiency is improved, but cache hit ratios decrease due to lack of data locality
Solution Approach 1:
The patent segments network flows as distinct entities and assigns each segment to a specific processing unit for consistent handling. By segmenting the workload at the flow level rather than distributing individual packets randomly, the system maintains data locality within each processing unit's cache while still achieving parallel processing across multiple units. This segmentation resolves the contradiction by preserving cache efficiency alongside parallel processing benefits.
Data Source
AI summary
An integrated circuit for distributing processing tasks includes a pre-selector circuit and a scheduler circuit. The pre-selector circuit is configured to receive a processing task, determine a category of the processing task, and select, from a set of task distribution techniques and based at least in part on the category of the processing task, a task distribution technique for distributing the processing task to a group of processing units. The scheduler circuit is configured to implement the selected task distribution technique to select, from the group of processing units, a target processing unit for performing the processing task.