Task Flow Reordering Avoidance in Processor-Accelerator Transitions
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Solution Overview
Problem
In multitasking computer systems, out-of-order execution of tasks between software and hardware accelerators can lead to erroneous results, particularly in communication systems where packets are processed out of order, causing potential packet drops.
Innovation Solution
A control circuitry system that assigns initial tasks to processors for execution in normal mode and subsequent tasks to hardware accelerators, ensuring that accelerators only execute tasks after processors have completed their initial tasks by using unique ID codes to verify order, thereby preventing out-of-order execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If tasks are assigned to hardware accelerators for accelerated mode execution, then execution speed and productivity are improved, but out-of-order execution errors and reliability deteriorate
Solution Approach 1:
The patent introduces control circuitry as an intermediary component that sits between the task assignment mechanism and the execution units (processors and accelerators). This control circuitry monitors task IDs, verifies execution order, and prevents accelerators from executing tasks out of order. The intermediary layer enables accelerated execution while maintaining reliability by mediating the interaction between speed-optimized accelerators and order-critical task sequences.
Solution Approach 2:
The system implements a feedback mechanism where the control circuitry continuously monitors the execution status of tasks by comparing task IDs. When an accelerator completes a task, the control circuitry verifies that the task ID corresponds to the next expected task in sequence. This feedback loop ensures that even if accelerators complete tasks faster than processors, the system only proceeds when execution order is maintained, thus preserving reliability while allowing speed optimization.
2Reliability
If initial tasks are executed by processors in normal mode, then execution order reliability is maintained, but execution speed and productivity decrease
Solution Approach 1:
The patent segments the task execution workflow into distinct phases: initial tasks executed by processors in normal mode to establish correct execution order, followed by subsequent tasks executed by accelerators in accelerated mode. This segmentation allows the system to prioritize reliability for critical initial operations while maximizing speed for subsequent operations, thus resolving the contradiction between maintaining execution order and achieving high productivity.
Solution Approach 2:
The system performs preliminary action by having processors execute initial tasks in normal mode before accelerators take over. This preliminary execution phase ensures that the execution order is established and verified before transitioning to faster accelerated mode. The preliminary action of using processors first creates a reliable foundation that enables subsequent accelerated execution without compromising overall execution order accuracy.
3Productivity
If hardware accelerators execute subsequent tasks in accelerated mode, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent extracts the complexity of order verification and task coordination into a separate, dedicated control circuitry component. Rather than embedding complex verification logic within the accelerators or processors themselves, the system takes out the coordination function and places it in a specialized control unit. This extraction allows the execution units to remain simple and efficient while the control circuitry handles the complexity of maintaining execution order, thus achieving high productivity with manageable complexity distribution.
Data Source
AI summary
A computer system includes one or more processors, one or more hardware accelerators, and control circuitry. The processors are configured to run software that executes tasks in a normal mode. The accelerators are configured to execute the tasks in an accelerated mode. The control circuitry is configured to receive one or more flows of tasks for execution by the processors and the accelerators, assign one or more initial tasks of each flow for execution by the processors, assign subsequent tasks of each flow for execution by the accelerators, and verify, for each flow, that the accelerators do not execute the subsequent tasks of the flow until the processors have fully executed the initial tasks of the flow.