Software Framework Task Force for Multi-Core Accelerator Management

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Solution Overview

Problem

The existing methods for managing hardware accelerators, particularly in systems with multiple cores, lead to inefficient CPU cycle consumption and performance deterioration due to the need for continuous monitoring using polling methods, which increases the number of threads and resource waste.

Innovation Solution

A software framework that instantiates a task force with metadata configuration, registers tasks, and uses a core monitor to allocate tasks to available cores based on estimated time of arrival (ETA), allowing for efficient task management and reduced thread usage by prioritizing cores with shorter ETAs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the polling method is used to continuously monitor the state of cores until task completion, then the task state can be detected, but unnecessary CPU cycle consumption occurs and system efficiency deteriorates

Engineering Contradiction:
Improvetask state detectionVSAvoidsystem efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements periodic polling at predetermined time intervals instead of continuous monitoring. The processor wakes up at scheduled intervals to check task completion status, allowing it to enter low-power states between polls. This reduces CPU cycle consumption while still reliably detecting task completion events.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system pre-calculates expected task completion times and schedules polling activities accordingly. By knowing in advance when tasks should complete, the processor can optimize its monitoring schedule to check status at meaningful intervals rather than continuously, reducing unnecessary CPU cycles.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If all individual cores are monitored separately in a multi-core hardware accelerator, then each core state can be tracked, but the number of threads increases and system performance deteriorates

Engineering Contradiction:
Improvecore state monitoringVSAvoidnumber of threads
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the monitoring of multiple cores into a single unified thread. Instead of creating separate monitoring threads for each core, one thread collects completion status from all cores through a shared status register or memory location, significantly reducing thread overhead while maintaining complete core state visibility.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single monitoring thread is designed to handle status checks for all cores universally. It interfaces with a centralized status mechanism that aggregates information from all cores, allowing one thread to perform the function that would otherwise require multiple dedicated threads.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If a hardware accelerator with dozens to hundreds of cores is used to increase processing capacity, then task throughput improves, but thread management complexity and resource consumption increase

Engineering Contradiction:
Improvetask throughputVSAvoidthread management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent combines monitoring responsibilities for dozens or hundreds of cores into a single thread that uses efficient status checking mechanisms. This allows the system to scale to many cores without proportionally increasing thread management complexity, as the single thread leverages hardware-supported status aggregation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system uses periodic status checks at optimized intervals rather than continuous monitoring of each core. This approach allows efficient management of large numbers of cores by checking their status at predetermined times, reducing the computational overhead of monitoring while maintaining awareness of all core states.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20230342211A1Method and device for controlling hardware accelerator by using SW framework structure homogeneous multi-core accelerator for supporting acceleration of time-critical task
Publication Date: 2023.10.26 MOBILINT INC
  • US20230342211A1 patent drawing
  • US20230342211A1 patent drawing
  • US20230342211A1 patent drawing

AI summary

Disclosed is a hardware accelerator controlling method performed by a hardware accelerator controlling device including a hardware accelerator including at least one core and programing a time-critical task, and a software framework connected to the hardware accelerator including instantiating, by the software framework, a task force, which is a task management unit provided by the software framework, in an application, configuring metadata by using the instantiated task force in the application, and registering, by the application, the task force thus configured in the software framework.