Task Graph Processor Assignment for Manycore Data Transfer Bottlenecks

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Solution Overview

Problem

The increasing complexity of processor architectures, particularly the shift towards manycore designs, limits computing performance due to bottlenecks in data transfer rates between processors and memory, necessitating new approaches for Computer Aided Analysis (CAA) applications to optimize data organization and distribution across diverse multiprocessing environments.

Innovation Solution

A method and system that utilize cell and interface objects with related attributes to create a task graph, allowing flexible assignment of computational tasks to available processors, including CPUs and GPUs, to maximize data transfer rates and accommodate the complexity of manycore architectures, thereby optimizing performance in distributed multiprocessing environments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If manycore processor architectures are used to increase processing power, then computational capacity is improved, but data transfer bottlenecks between processors and memory worsen

Engineering Contradiction:
Improvecomputational capacityVSAvoiddata transfer rate
Core Design Contradiction:
PowerVSSpeed

Solution Approach 1:

The input source is segmented into data-oriented cell objects and interface objects with specific processing attributes. This segmentation allows computational tasks to be divided and assigned to different processors in the manycore environment, enabling parallel processing while managing data transfer loads more effectively across multiple processing units

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a task graph dimension that maps computational tasks to available processors. This additional dimensional layer allows the system to optimize data organization and processor assignment beyond the traditional processor-memory architecture, creating efficient data pathways through graphical processing units and other specialized processors

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Power

If diverse processor architectures (CPUs and GPUs) are utilized to enhance processing capabilities, then computational performance is improved, but system complexity increases

Engineering Contradiction:
Improvecomputational performanceVSAvoidsystem complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The cell and interface object framework provides a universal interface that can be assigned to different processor types (CPUs, GPUs, and other processors). This multi-functional approach allows the same data structure and task assignment mechanism to work across diverse architectures, reducing the complexity that would otherwise arise from handling each processor type separately

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The task graph acts as an intermediary layer between the input source and the diverse processor architectures. It translates computational requirements into processor-specific assignments, managing the complexity of coordinating different processor types while maximizing their combined computational performance

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If data is reorganized to maximize data throughput in manycore environments, then computing performance is improved, but data organization complexity increases

Engineering Contradiction:
Improvecomputing performanceVSAvoiddata organization complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Different data organization strategies are applied locally to different types of processors. Cell objects and interface objects are organized and assigned based on the specific characteristics and optimal data structures for each processor type, allowing each processor to operate with data organized for its specific strengths while maintaining overall system coherence

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9032405B2Systems and method for assigning executable functions to available processors in a multiprocessing environment
Publication Date: 2015.05.12 ENVENIO INC
  • US9032405B2 patent drawing
  • US9032405B2 patent drawing
  • US9032405B2 patent drawing

AI summary

A computer implemented method for assigning executable functions to available processors in a Multiprocessor environment comprising (as an example of a collection of different processing architectures) one or more CPUs and one or more GPUs, the method comprising: providing an input source comprising instructions and data; breaking the input source into data oriented cell and interface objects with processing attributes; assigning the cell and interface objects to one or more of the GPUs and CPUs based on processing attributes and the multiprocessor environment; and producing output data.