Task Process Table for Hardware Control Flow
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Solution Overview
Problem
In wireless mobile communication systems, particularly in TD-SCDMA mobile communication base band processing, it is challenging to design hardware that fully satisfies complex algorithm flows due to difficulties in controlling the entire data processing flow using traditional counter-based control signals.
Innovation Solution
The method involves dividing tasks into sub-processes, determining a task process table based on the number of sub-processes and their clock cycles, and systematically controlling hardware units to perform these sub-processes in a specific order, allowing for precise control of the hardware processing flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional counter-based control signals are used to control hardware processing flow, then the hardware circuit can be designed based on given algorithms, but it becomes very difficult to implement complex algorithm flows such as TD-SCDMA multi-cell joint detection
Solution Approach 1:
The patent segments the complex algorithm flow into multiple discrete task states (e.g., state 0 for midamble reception, state 1 for FFT transformation, state 2 for interference elimination, etc.). Each state corresponds to a specific processing stage, allowing the complex multi-cell joint detection algorithm to be broken down into manageable, controllable units that can be systematically implemented in hardware.
Solution Approach 2:
The patent introduces a task process table as an intermediary control mechanism between the hardware circuit and the algorithm flow. This table stores pre-defined task states and control signals, acting as a mediator that translates complex algorithm requirements into simple hardware control operations, thereby resolving the difficulty of controlling complex data processing flows.
2Speed
If hardware processing cycle is predetermined based on algorithm analysis, then real-time data processing can be achieved, but it is difficult to satisfy the entire algorithm flow process in complex scenarios
Solution Approach 1:
The patent performs preliminary analysis of the algorithm flow beforehand to identify all necessary processing stages and their corresponding hardware requirements. The task process table is pre-configured with all task states and control signals needed for the complete algorithm flow, ensuring that when the hardware operates in real-time, all algorithm steps are reliably executed without omission.
Solution Approach 2:
The patent implements a dynamic state transition mechanism where the hardware processing cycle adapts to different task states. Instead of a fixed predetermined cycle, the system dynamically transitions between states (state 0 → state 1 → state 2 → ... → state 7) based on the algorithm flow requirements, allowing flexible adjustment of processing timing while maintaining real-time performance.
3Adaptability or versatility
If more hardware units are added to handle complex algorithm flows, then the algorithm implementation becomes more complete, but the control flow becomes even more difficult to manage
Solution Approach 1:
The patent designs a universal task process table that can control multiple hardware units (FFT processor, interference eliminator, channel estimator, etc.) through a unified state-based interface. Each hardware unit responds to standardized control signals from the task process table, allowing diverse hardware components to be managed through a single universal control mechanism, thereby simplifying operation despite increased hardware complexity.
Data Source
AI summary
Disclosed is a method for implementing task-process-table based hardware control, which includes dividing a task that has to be implemented by a hardware circuit into multiple sub-processes, and determining the depth of the task process table according to the number of the sub-processes; according to the control information of the hardware unit corresponding to each sub-process and the number (SPAN) of clock cycles occupied by hardware processing for the sub-process, determining the bit width of the task process table and generating the task process table; starting the hardware unit corresponding to each sub-process in an order of the sub-processes, under the control of the control information in the task process table, and completing the processing of each sub-process. A device for implementing hardware control is also disclosed. The disclosure enables precise control of the hardware control flow and is of versatility. For the hardware implementation of a task with a complex algorithm flow, the data processing flow is accurate, and the development efficiency is improved.