Task Processor Hardware Registers for Fast Interrupt Handling
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Solution Overview
Problem
Real-time operating systems (RTOS) face significant performance issues due to overhead incurred during task switches, which can impact their ability to respond quickly to external events such as interrupt requests, especially in embedded systems with severe time requirements.
Innovation Solution
A task processor with a processing register, execution control circuit, state register, task switching circuit, task selecting circuit, and interrupt circuit is implemented to efficiently manage task execution and interrupt processing, allowing for high-speed task switching and interrupt handling by loading and saving task data directly in hardware registers, reducing reliance on context information stored in memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If context information is saved and loaded in memory during task switching, then task execution can be maintained across time slices, but system overhead increases and response speed to interrupts decreases
Solution Approach 1:
The patent extracts the context information storage from main memory and places it in hardware registers (TCB registers) that are part of the CPU architecture. This removes the bottleneck of memory access during task switches, allowing context to be saved and loaded in hardware rather than through software memory operations, thereby reducing overhead while maintaining execution continuity.
Solution Approach 2:
The patent introduces TCB (Task Control Block) registers as an intermediary between the CPU and the task context. These registers act as a buffer that holds task context information locally, eliminating the need to access main memory during task switches. The TCB registers serve as a mediator that enables fast context transfer while maintaining the abstraction of task management.
2Adaptability or versatility
If traditional interrupt processing is used with software-based task switching, then system flexibility is maintained, but interrupt response time is delayed due to context saving and loading overhead
Solution Approach 1:
The patent performs preliminary action by pre-configuring TCB registers to hold task context information before interrupts occur. When an interrupt happens, the system can immediately access the pre-loaded context in hardware registers rather than performing full context saving and loading sequences, enabling faster interrupt response while maintaining system flexibility through the same hardware architecture.
Solution Approach 2:
The patent substitutes the software-based mechanical process of context saving/loading with a hardware-level register transfer mechanism. By replacing software memory operations with hardware register transfers, the system achieves faster interrupt response times while preserving the flexible task switching capabilities through the same architectural framework.
3Speed
If hardware registers are used to store task context instead of memory, then task switching speed increases, but hardware complexity increases
Solution Approach 1:
The patent applies universality by designing TCB registers that serve multiple functions: they store task context information, manage task state, and facilitate both voluntary task switching and interrupt-driven context changes. This multi-functional register design achieves fast task switching without requiring separate dedicated hardware for each function, thereby limiting the increase in hardware complexity while maximizing speed benefits.
Data Source
AI summary
A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.