Task-Retention Register Structure for Low-Power Semiconductor Cores
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Solution Overview
Problem
Semiconductor devices face challenges in reducing power consumption and circuit layout area while maintaining computing performance, particularly in CPUs, due to the need for multiple register banks and peripheral circuits that are not always active, leading to energy consumption and increased layout area.
Innovation Solution
Incorporating a state control portion with a processor core that includes an arithmetic portion and register portion, utilizing flip-flops with silicon transistors and data retention circuits with oxide semiconductors to manage data retention and switching between tasks, and implementing a control system for power gating of peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple register banks are prepared to execute multiple tasks, then computing performance is improved, but circuit layout area increases
Solution Approach 1:
The patent transitions from a planar arrangement of multiple register banks to a three-dimensional stacked structure where register banks are arranged in vertical layers. This dimensional change allows multiple register banks to coexist without proportionally increasing the planar circuit layout area, thus maintaining high computing performance while reducing area consumption.
Solution Approach 2:
The patent implements a nested structure where register banks are stacked vertically within a compact footprint. The first register bank is positioned in a first region and the second register bank in a second region above or below it, creating a nested arrangement that maximizes space utilization and reduces overall circuit layout area while preserving multiple task execution capabilities.
2Use of energy by moving object
If peripheral circuits are power gated to reduce power consumption, then energy efficiency is improved, but setting data must be re-stored in setting registers upon return, causing loss in power gating effect
Solution Approach 1:
The patent stores setting data for peripheral circuits in retention memory circuits that maintain data even when power is reduced. This preliminary action ensures that when peripheral circuits return from power gating state, the setting data is already preserved and ready for immediate use, eliminating the need to re-store settings and maintaining the energy savings benefits of power gating.
Solution Approach 2:
The patent introduces retention memory circuits as an intermediary between the power gating control and the peripheral circuits. These retention memory circuits act as a mediator that preserves setting data during power gating transitions, allowing peripheral circuits to be powered down without losing their configuration data, thus maintaining power gating effectiveness.
3Productivity
If data is written to external memory when register bank is insufficient, then task execution capability is maintained, but energy is consumed for writing and reading data between external memory and register
Solution Approach 1:
The patent resolves the register bank insufficiency by utilizing vertical stacking in three-dimensional space rather than expanding horizontally. Multiple register banks are arranged in stacked regions, providing sufficient registers for all tasks without requiring external memory, thereby eliminating the energy consumption associated with data transfers between external memory and registers while maintaining full task execution capability.
Data Source
AI summary
A semiconductor device with a novel structure is provided. The semiconductor device includes a register. The register includes a flip-flop and a plurality of data retention circuits. The flip-flop includes a first transistor in which a semiconductor layer including a channel formation region is silicon, an input terminal of the flip-flop is electrically connected to each of output terminals of the data retention circuits, and an output terminal of the flip-flop is electrically connected to each of input terminals of the data retention circuits. The data retention circuits include a second transistor in which a semiconductor layer including a channel formation region is an oxide semiconductor, and when the second transistor is in a non-conduction state, the data retention circuits have a function of retaining a potential corresponding to data corresponding to a plurality of tasks. A state control portion rewrites data that the flip-flop has on the basis of data retained in the data retention circuits in accordance with the plurality of tasks executed by a processor core.