Task Scheduler Device for Low-Latency Power Management
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Solution Overview
Problem
In systems requiring real-time capability, such as base stations, the transition of CPU cores to deep idle states leads to extended latency times during task restoration, compromising low-latency operations while attempting power saving.
Innovation Solution
A task scheduler device that continuously allocates tasks to a core or core group of the processor based on the processor's use rate, preventing transitions to deep idle states and reducing restoration latency, while allowing other CPU cores to transition to deep idle states for power saving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If CPU cores transition to deep idle states for power saving, then power consumption is reduced, but restoration latency increases
Solution Approach 1:
The patent segments CPU cores into two groups: active core groups that continuously execute tasks and remain in shallow idle states, and inactive cores that transition to deep idle states for power saving. This segmentation resolves the contradiction by allowing different idle state behaviors for different core groups based on their task allocation status.
Solution Approach 2:
The task scheduler continuously allocates tasks to active core groups to prevent them from transitioning to deep idle states. By maintaining continuous task allocation as a preliminary action, the system ensures that active cores remain in a ready state with minimal restoration latency while inactive cores can deeply sleep.
2Loss of time
If CPU cores remain in active state to reduce restoration latency, then real-time capability is improved, but power consumption increases
Solution Approach 1:
The patent divides CPU cores into active and inactive groups, allowing active cores to remain in low-latency states while inactive cores enter deep power-saving states. This segmentation enables the system to achieve both low restoration latency for active cores and reduced power consumption for inactive cores simultaneously.
Solution Approach 2:
Different idle state qualities are applied to different CPU core groups based on their local task allocation status. Active core groups maintain shallow idle states with fast restoration characteristics, while inactive cores use deep idle states with maximum power saving characteristics. This local quality differentiation resolves the global contradiction.
3Loss of time
If tasks are continuously allocated to CPU cores, then restoration latency is reduced, but task scheduling complexity increases
Solution Approach 1:
The task scheduler manages complexity by segmenting CPU cores into active and inactive groups with different scheduling policies. Active core groups receive continuous task allocation to maintain low latency, while inactive cores are left unallocated to enable deep idle transitions. This segmented management approach keeps scheduling complexity manageable.
Solution Approach 2:
The system dynamically adjusts the classification of CPU cores between active and inactive groups based on task arrival patterns and load conditions. This dynamic adaptation allows the scheduler to optimize the balance between restoration latency and scheduling complexity in real-time without requiring complex static configurations.
Data Source
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AI summary
A task scheduler device (100, 100A) that, in a calculation system (1000) that reduces power consumption by reducing stepwise an operation state of a processor according to a processing load, allocates tasks to a core group of the processor, task scheduler device (100, 100A) including: a task amount/period prediction part (122) that acquires a use rate of the processor, and a task CPU allocation part (123) that, based on the use rate of the processor acquired by the task amount/period prediction part (122), continuously allocates tasks to a core or a core group of the processor to be used at a predetermined frequency or more.