Task Scheduler Priority Inheritance for Multiprocessor Power Optimization

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Solution Overview

Problem

Existing task scheduler mechanisms for multiprocessor systems fail to properly assign tasks between high-performance and low-power-consumption processors, leading to inefficient performance and excessive power consumption, as they do not consider the shared usage of tasks by multiple applications and the varying performance characteristics of tasks.

Innovation Solution

A task scheduler mechanism that includes a synchronization mechanism to inherit priority from driving tasks and a task assignment mechanism to dynamically assign tasks to either the high-performance or low-power-consumption processor based on inherited priority, load, and power status, using management tables to manage task priorities and processor allocation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a task is assigned to the high-performance processor to ensure performance, then processing speed is improved, but power consumption increases

Engineering Contradiction:
Improveprocessing speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The system dynamically selects between high-performance and low-power processors based on real-time task characteristics and system state. The task assignment mechanism continuously evaluates task priority, processor availability, and power management policies to make adaptive decisions, allowing the system to switch processor assignments without manual intervention or system reconfiguration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the assignment parameter (which processor executes the task) based on task priority and system conditions. High-priority tasks are assigned to the high-performance processor to maximize speed, while lower-priority tasks are assigned to the low-power processor to reduce energy consumption, thereby optimizing the balance between processing speed and power usage.

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If a task is assigned to the low-power-consumption processor to reduce energy usage, then power consumption is reduced, but processing speed decreases

Engineering Contradiction:
Improvepower consumptionVSAvoidprocessing speed
Core Design Contradiction:
Use of energy by moving objectVSSpeed

Solution Approach 1:

The system dynamically adjusts task assignment based on real-time conditions. When power savings are prioritized and the task can tolerate lower processing speed, the system assigns the task to the low-power processor. This dynamic decision-making ensures that speed is not unnecessarily sacrificed when energy efficiency is the primary goal.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the assignment parameter based on power management requirements. For non-critical tasks or during low-power modes, the system assigns tasks to the low-power processor, accepting reduced speed in exchange for energy savings. This parameter change allows flexible trade-offs between power consumption and processing speed.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If task priorities are dynamically manipulated to perform scheduling, then scheduling flexibility is improved, but system complexity increases

Engineering Contradiction:
Improvescheduling flexibilityVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The scheduling system is segmented into distinct functional modules: a synchronization mechanism for priority inheritance, a task assignment mechanism for processor selection, and management tables for state tracking. This segmentation allows each module to handle specific aspects of scheduling independently, reducing overall system complexity while maintaining flexibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediary structures (synchronization mechanisms and management tables) that mediate between task requirements and processor capabilities. These intermediaries simplify the scheduling logic by providing standardized interfaces and centralized state management, reducing the complexity of direct task-to-processor matching while enabling flexible priority-based scheduling.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9513974B2Task scheduler mechanism, operating system, and multiprocessor system
Publication Date: 2016.12.06 RENESAS ELECTRONICS CORP
  • US9513974B2 patent drawing
  • US9513974B2 patent drawing
  • US9513974B2 patent drawing

AI summary

In a multiprocessor system having a high-performance processor and a low-power-consumption processor, tasks are properly assigned to the high-performance processor or to the low-power-consumption processor even if the tasks include those commonly used by a plurality of applications. The applications each include a plurality of tasks that are driven by an input or sequentially driven by another task. A task scheduler mechanism includes a synchronization mechanism that causes a driven task to inherit a priority assigned to the input or a synchronizing task, and a task assignment mechanism that determines in accordance with the inherited priority whether to assign the driven task to the high-performance processor or to the low-power-consumption processor.