Task Scheduling Circuitry for Homogeneous Processor Cores

Solution Overview

Problem

The increasing number of processor cores on a System on Chip (SoC) complicates task scheduling due to slight differences in physical circuit implementation properties among logically homogeneous cores, leading to inefficiencies in performance and energy consumption.

Innovation Solution

The task scheduling circuitry allocates tasks based on physical circuit implementation properties such as heat dissipation ability, performance maintenance duration, position on the chip, and susceptibility to voltage droops, to optimize task distribution among processor cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of processor cores on a SoC is increased to meet performance demand, then the processing capability and performance are improved, but the task scheduling complexity increases due to slight differences in physical circuit implementation properties among logically homogeneous cores

Engineering Contradiction:

Improveprocessing capabilityVSAvoidtask scheduling complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies local quality by recognizing and utilizing the slight physical differences between individually manufactured processor cores. Each core's specific physical properties (such as variations in transistor characteristics or circuit implementation) are taken into account during task scheduling, allowing tasks to be optimally distributed based on the unique characteristics of each core rather than treating all cores as identical.

Inventive Principle:

Principle #3Local quality

2Ease of operation

If tasks are allocated to processor cores without considering physical circuit implementation properties, then the scheduling process is simplified, but performance and energy consumption efficiency deteriorate

Engineering Contradiction:

Improvescheduling simplicityVSAvoidperformance efficiency

Core Design Contradiction:

Ease of operationVSProductivity

Solution Approach 1:

The patent applies parameter changes by incorporating physical circuit implementation properties as scheduling parameters. The scheduling mechanism considers specific physical parameters of each processor core (such as variations in switching characteristics, power consumption, or thermal properties) and adjusts task allocation decisions based on these parameters, thereby optimizing both performance and energy efficiency.

Inventive Principle:

Principle #35Parameter changes

3Device complexity

If physically different processor cores are treated as identical for scheduling purposes, then the scheduling algorithm is simpler, but energy consumption increases due to suboptimal task distribution

Engineering Contradiction:

Improvescheduling algorithm complexityVSAvoidenergy consumption

Core Design Contradiction:

Device complexityVSLoss of energy

Solution Approach 1:

The patent applies local quality by recognizing and utilizing the slight physical differences between individually manufactured processor cores. Each core's specific physical properties (such as variations in transistor characteristics or circuit implementation) are taken into account during task scheduling, allowing tasks to be optimally distributed based on the unique characteristics of each core rather than treating all cores as identical.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250013491A1Determining whether a given task is allocated to a given one of a plurality of logically homogeneous processor cores

Publication Date: 2025.01.09 ARM LTD

AI summary

A system on chip (102) comprising a plurality of logically homogeneous processor cores (104), each processor core comprising processing circuitry (210) to execute tasks allocated to that processor core, and task scheduling circuitry (202) configured to allocate tasks to the plurality of processor cores. The task scheduling circuitry is configured, for a given task to be allocated, to determine, based on at least one physical circuit implementation property associated with a given processor core, whether the given task is allocated to the given processor core.