Task Scheduling Method for Heterogeneous Chips

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Solution Overview

Problem

Current task scheduling methods in heterogeneous computing architectures face high IO delays and high data cache and bandwidth requirements, limiting their effectiveness in complex scenarios, and lack versatility due to fixed data flow connections between sub-engines.

Innovation Solution

A task scheduling method that divides tasks into sub-tasks with defined start phases, allowing sub-tasks to overlap chronologically, using an interconnection bus for communication between a parser, scheduler, and sub-engines, and implementing counters for passive flow control to reduce cache and bandwidth needs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If tasks are executed sequentially with fixed data flow connections between sub-engines, then the system structure is simple, but the overall delay is high and versatility is limited

Engineering Contradiction:
Improveoverall delayVSAvoidscheduling system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments tasks into multiple sub-tasks that can be independently scheduled on different sub-engines. Each sub-task has a defined start phase, allowing flexible scheduling independent of fixed data flow connections. This segmentation enables parallel execution and reduces overall delay while maintaining manageable system complexity through structured task decomposition.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic scheduling where the scheduler can arbitrarily assign sub-tasks to sub-engines based on real-time status and phase information. The system transitions from static fixed connections to dynamic flexible scheduling, allowing the scheduling order to be adjusted according to sub-engine availability and task dependencies, thereby reducing delay without requiring complex hardware reconfiguration.

Inventive Principle:
Principle #15Dynamics

2Loss of time

If sub-tasks are executed with overlapping time, then the overall delay is reduced, but the data flow management becomes complex

Engineering Contradiction:
Improveoverall delayVSAvoiddata flow management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms where sub-engines notify the scheduler when they complete sub-tasks or become available. The scheduler uses this feedback information to make informed scheduling decisions, allowing overlapping execution while maintaining proper data flow management. The feedback loop enables the system to coordinate complex overlapping operations without requiring overly complicated manual management.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs preliminary actions by pre-defining start phases for each sub-task and pre-establishing the sub-task list with dependency information. This preliminary structuring allows the scheduler to plan overlapping executions in advance, reducing the need for complex real-time coordination while still achieving time overlap benefits.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If traditional task scheduling is used, then the system is easy to implement, but cache and bandwidth requirements are high

Engineering Contradiction:
Improvesystem implementation easeVSAvoidcache and bandwidth requirements
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent applies partial action by loading only the necessary data into sub-engine caches based on the specific sub-tasks being executed, rather than pre-loading all data. The scheduler manages cache requirements selectively, loading data only when needed for upcoming sub-tasks. This partial loading approach reduces overall cache and bandwidth requirements while maintaining implementation simplicity through automated scheduler coordination.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20240143392A1Task scheduling method, chip, and electronic device
Publication Date: 2024.05.02 INSPUR SUZHOU INTELLIGENT TECH CO LTD
  • US20240143392A1 patent drawing
  • US20240143392A1 patent drawing
  • US20240143392A1 patent drawing

AI summary

The preset application discloses a task scheduling method, including: in response to receiving an issued task, dividing, by a parser, the task into sub-tasks and generating a sub-task list, a task parameter corresponding to each sub-task is recorded in the sub-task list, the task parameter includes a start phase of a next sub-task; sending, by a scheduler, the task parameter of a sub-task to be processed in the sub-task list to a corresponding sub-engine; executing, by the corresponding sub-engine, a corresponding sub-task to be processed; sending a notification to the scheduler in response to an operating phase when the corresponding sub-engine executes the corresponding sub-task to be processed being the same as the start phase in the received task parameter; and in response to the notification being detected by the scheduler, returning to the step of sending the task parameter of a sub-task to be processed to a corresponding sub-engine.