Task Scheduling Using Voltage Regulator Efficiency
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Solution Overview
Problem
Current task scheduling methods in computing devices do not effectively minimize total power consumption by not considering the efficiency of voltage regulators when selecting cores for task execution, leading to suboptimal energy usage.
Innovation Solution
A method and system for regulator efficiency-aware task scheduling that identifies candidate processors, determines task scheduling cases based on voltage regulator input power levels and efficiency, and selects the case with the lowest total regulator input power for executing tasks, thereby optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional task scheduling methods are used that only consider processing load and performance, then task execution speed is maintained, but total power consumption is not minimized due to ignoring voltage regulator efficiency
Solution Approach 1:
The system pre-calculates and stores voltage regulator efficiency data for different operating conditions before task scheduling occurs. This preliminary preparation allows the scheduler to quickly access efficiency information without performing complex real-time calculations, thereby reducing scheduling complexity while enabling energy-optimized task placement
Solution Approach 2:
The patent introduces voltage regulator efficiency metrics as an intermediary parameter that bridges task scheduling decisions and power consumption outcomes. By incorporating this intermediate efficiency measurement, the system can make informed scheduling decisions that minimize total power consumption without directly controlling voltage regulator operations
2Productivity
If tasks are distributed across multiple cores to balance load, then processing throughput is improved, but voltage regulator efficiency is not optimized leading to higher overall power consumption
Solution Approach 1:
The system dynamically changes task scheduling decisions based on voltage regulator efficiency parameters. By monitoring and responding to changes in regulator efficiency under different load conditions, the scheduler can adjust task distribution to maintain high processing throughput while minimizing energy losses in the voltage regulation process
Solution Approach 2:
The patent implements a feedback mechanism where voltage regulator efficiency measurements are continuously monitored and fed back to the task scheduler. This feedback loop enables the system to adapt task distribution in response to changing efficiency conditions, optimizing the balance between processing throughput and power consumption
Data Source
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AI summary
Task scheduling in a computing device may be based in part on voltage regulator efficiency. For an additional task to be scheduled, multiple task scheduling cases may be determined that represent execution of the additional task on each of a number of processors concurrently with one or more other tasks executing among the processors. For each task scheduling case, a regulator input power level for a voltage regulator may be determined based on a performance level indication associated with the additional task, the one or more other tasks executing on the processors, and the efficiency level of each voltage regulator. For each task scheduling case, a total regulator input power level may be determined by summing the regulator input power levels for all voltage regulators. The additional task may be executed on a processor associated with a task scheduling case for which total regulator input power is lowest.