Task Server Interface for Logic Verification Speed

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Solution Overview

Problem

Current logic verification systems face challenges in implementing a task-based interface between a test bench and a design under verification due to issues like dynamic thread creation and unknown caller processes, which hinder efficient communication and execution.

Innovation Solution

A method and apparatus that utilize a task server and context memory in a hardware accelerator, with a task stub in the computer to manage remote procedure calls, allowing for efficient communication and execution of threads by transferring input arguments and triggering execution using RPC channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a task interface is used between test bench and DUV, then communication speed increases significantly, but technical challenges prevent implementation due to dynamic thread creation and unknown caller processes

Engineering Contradiction:
Improvecommunication speedVSAvoidinterface implementation complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent introduces a task server as an intermediary component that mediates between the test bench and DUV. The task server receives task calls from the test bench, manages thread creation and execution, and communicates with the DUV, thereby isolating the complexity of dynamic thread management from the interface definition and enabling high-speed communication without direct exposure to implementation complexities

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the verification system into distinct functional components: test bench, task server, and DUV. Each component has a specific responsibility - the test bench initiates tasks, the task server manages execution and threading, and the DUV performs verification. This segmentation allows the task interface to achieve high communication speed while the task server handles the complexity of dynamic thread creation and management separately

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple processes call the same task instance concurrently, then verification productivity increases, but the unknown number of calling processes creates implementation difficulties

Engineering Contradiction:
Improveverification productivityVSAvoidtask management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic thread management in the task server that can adapt to any number of concurrent calling processes. The task server dynamically creates and manages threads based on the actual number and pattern of calls received from multiple processes, rather than requiring a fixed or predetermined number of callers. This dynamic approach enables high verification productivity through concurrent execution while the task server internally manages the complexity of handling an unknown number of processes

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If task definition consumes simulation time, then task interface functionality is achieved, but overall verification speed is reduced due to compilation overhead

Engineering Contradiction:
Improvetask interface functionalityVSAvoidsimulation time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent performs task definition and compilation in advance during the test bench compilation phase, before simulation begins. The task server is pre-configured with task definitions, and the interface is established beforehand. During actual simulation, the pre-compiled task interface enables high-speed communication without consuming simulation time, as the compilation overhead has already been completed in the preliminary setup phase

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8161502B2Method and apparatus for implementing a task-based interface in a logic verification system
Publication Date: 2012.04.17 CADENCE DESIGN SYST INC
  • US8161502B2 patent drawing
  • US8161502B2 patent drawing
  • US8161502B2 patent drawing

AI summary

Method and apparatus for implementing a task-based interface in a logic verification system is described. In some examples, a task server and a context memory are implemented in a hardware accelerator for a task. The task server is configured for communication with the logic design. A task stub configured for execution by a computer for the task is generated. Calls to the task are received from a test bench in the computer at the task stub. Remote procedure call (RPC) channels are established in response to the calls. Values of input arguments for the calls are transferred to the context memory through the RPC channels. Execution of threads of the task in the task server is triggered using the values of the input arguments in the context memory as parametric input.