Through-Array-Vias in Memory Arrays Using Sacrificial Plugs
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Solution Overview
Problem
Current methods for forming memory arrays and conductive through-array-vias (TAVs) face challenges in efficiently integrating conductive materials and structures within vertically-stacked memory cell architectures, particularly in ensuring direct electrical coupling and precise etching processes to maintain data storage and access functionality.
Innovation Solution
The method involves forming a stack with alternating insulative and wordline tiers, using a mask to create trench and TAV openings, and then forming conductive material within these openings to establish operative TAVs, while also forming channel-material strings and wordline-intervening structures to support memory cell operation, employing 'gate-last' or 'replacement-gate' processing techniques to ensure accurate and efficient integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form conductive materials in vertically-stacked memory arrays, then manufacturing process complexity increases, but electrical coupling efficiency and precision deteriorate
Solution Approach 1:
The patent applies preliminary action by forming sacrificial plugs in TAV openings before forming the memory cell stacks. This allows the conductive material pathways to be pre-established through the entire vertical stack, ensuring precise electrical coupling without requiring complex post-formation alignment processes. The sacrificial plugs are later removed and replaced with conductive material, achieving high precision electrical coupling while maintaining manageable manufacturing complexity.
Solution Approach 2:
The patent segments the manufacturing process into distinct phases: forming sacrificial plugs, building memory cell stacks, removing sacrificial plugs, and filling TAV openings with conductive material. This segmentation allows each step to be optimized independently, improving electrical coupling efficiency through precise control of conductive pathway formation while keeping overall process complexity manageable through systematic breakdown of operations.
2Manufacturing precision
If precise etching processes are used to form TAV openings, then manufacturing precision improves, but processing time increases
Solution Approach 1:
The patent performs preliminary etching to form TAV openings through the entire vertical stack before completing the memory cell formation. This allows precise etching to be done on a relatively shallow depth at one time, achieving high manufacturing precision without requiring excessively long processing times that would result from forming openings through the entire stack height after all layers are deposited.
Solution Approach 2:
The etching process is segmented into multiple stages: forming initial TAV openings, forming memory cell structures, and performing additional etching steps as needed. This segmentation allows precise etching to be distributed across multiple shorter processing steps rather than requiring one extremely long etching cycle, thereby maintaining high precision while reducing total processing time.
3Quantity of substance
If vertically-stacked memory cell architectures are used, then data storage density improves, but integration of conductive materials becomes more difficult
Solution Approach 1:
The patent applies preliminary action by forming sacrificial plugs in TAV openings that extend through the entire vertical stack before memory cell formation. This pre-establishes the conductive material pathways needed for high-density vertical architecture, making the subsequent integration of conductive materials straightforward rather than difficult, as the pathways are already defined and ready to be filled.
Solution Approach 2:
The patent uses sacrificial plugs as intermediary structures during manufacturing. These temporary structures facilitate the integration of conductive materials in vertically-stacked architectures by providing defined pathways that are later replaced with actual conductive materials. This intermediary approach simplifies the integration process compared to attempting to directly form conductive pathways through complex multi-layer vertical structures.
Data Source
AI summary
A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.