TCAM Entry Coding for On-the-Fly Error Correction

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Solution Overview

Problem

Ternary Content Addressable Memories (TCAMs) face challenges in error detection and correction due to their ternary nature, making it difficult to implement reliable error correction techniques without excessive overhead or restrictive usage limitations, especially in sensitive networking applications prone to single-event upsets.

Innovation Solution

The implementation of error detection and correction codes that encode values in a way to ensure a minimum distance between encoded states, allowing for single-error correction and double-error detection, along with segregated entry groups and independent encoding for each entry group, enables reliable operation and tolerance for errors in TCAMs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional error detection and correction techniques are used in TCAMs, then reliability is improved, but device complexity and overhead increase significantly

Engineering Contradiction:
Improveerror detection and correction capabilityVSAvoidoverhead in storage bits
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the TCAM into multiple banks, with each bank containing a subset of the encoded comparison values. This segmentation allows error correction to be performed independently in each bank, reducing the overall complexity and overhead compared to encoding the entire TCAM content in a single error correction code structure.

Inventive Principle:
Principle #1Segmentation

2Reliability

If error correction codes are implemented in TCAMs, then reliability is improved, but restrictions are imposed on where values can be stored

Engineering Contradiction:
Improveerror correction capabilityVSAvoidflexibility in data storage location
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent employs a universal error correction code structure that can be applied to any comparison value stored in any bank of the TCAM. The encoding scheme and error correction logic are designed to work uniformly across all banks, allowing values to be stored and corrected in any location without requiring location-specific error correction mechanisms.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If background scrubbing is used to detect errors in TCAMs, then some errors are detected, but errors may not be detected before errored data is used

Engineering Contradiction:
Improveerror detection capabilityVSAvoidtime delay in error detection
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent encodes the comparison values with error detection and correction codes before they are stored in the TCAM banks. This preliminary encoding ensures that when values are read or searched, the error correction can be performed immediately on-the-fly, detecting and correcting errors before the data is used for routing decisions, eliminating the delay associated with background scrubbing operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7689889B2Content addressable memory entry coding for error detection and correction
Publication Date: 2010.03.30 CISCO TECHNOLOGY INC
  • US7689889B2 patent drawing
  • US7689889B2 patent drawing
  • US7689889B2 patent drawing

AI summary

A Content Addressable Memory (CAM) or Ternary CAM (TCAM) provides error detection and correction (EDAC). EDAC codes are chosen based on logical and physical properties of the CAM/TCAM. An entry in the CAM/TCAM comprises a plurality of groups, each group comprising a plurality of storage bits. Writes to the storage bits are encoded to enable EDAC. Lookup data is divided into lookup groups of one or more bits, and is applied to corresponding groups of entries to be searched. In one embodiment, storage bits in a group are first decoded to detect and/or to correct errors and then compared with a lookup group to produce a hit indication. In another embodiment, storage bits in a group are logically combined with a lookup group to produce a hit indication, wherein a correctable error in the storage bits does not affect correctness of the hit indication.