Protocol-Independent Packet Routing via TCAM and Hashing

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Solution Overview

Problem

Most application-specific integrated circuits (ASICs) in Network Interface Controllers (NICs) can only recognize a limited number of protocols, leading to slower processing of unsupported protocols and resulting in processing bottlenecks and under-utilization of network bandwidth.

Innovation Solution

A method and system utilizing a ternary content-addressable memory (TCAM), a first static random access memory (SRAM), and a second SRAM to identify and route data packets based on protocol-independent routing, where the TCAM matches packet headers to determine an initial routing instruction, and the SRAM provides partial routing information used to generate a hash value for final routing decisions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If ASICs in NICs recognize only a limited number of protocols, then device complexity is reduced and manufacturing is easier, but processing speed for unsupported protocols decreases and processing bottlenecks occur

Engineering Contradiction:
Improvepacket processing rateVSAvoidprotocol support capability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements a universal routing architecture that can handle multiple network protocols (IPv4, IPv6, MPLS, Ethernet, etc.) through a single unified processing path. The content-addressable memory and hash-based routing mechanism are protocol-agnostic, allowing the same hardware infrastructure to process different protocol types at full line rate without requiring protocol-specific ASIC logic for each protocol variant.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system changes the routing lookup parameter from protocol-specific header formats to a unified hash value derived from packet content. By hashing relevant packet fields and using the hash as an index into the content-addressable memory, the system transforms protocol-specific routing lookups into a protocol-independent process, enabling high-speed processing of diverse protocols through the same mechanism.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If ASICs process only supported protocols at high speed, then processing efficiency for those protocols is improved, but network bandwidth utilization decreases due to bottlenecks on unsupported protocols

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidbandwidth utilization
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The routing architecture provides universal high-speed processing capability for all supported protocols by eliminating protocol-specific processing paths. The content-addressable memory and hash-based lookup mechanism handle IPv4, IPv6, MPLS, and other protocols through the same efficient hardware path, ensuring that bandwidth utilization is maximized regardless of the protocol being processed.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If firmware processes unsupported protocols, then adaptability to new protocols is improved, but processing speed decreases significantly compared to ASIC processing

Engineering Contradiction:
Improveprotocol compatibilityVSAvoidprocessing speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent introduces an intermediary hashing mechanism that bridges between the protocol-independent input and the content-addressable memory. By hashing packet fields and using the hash as an index, the system creates a universal interface that works for all protocols without requiring firmware intervention, maintaining ASIC-speed processing while achieving protocol independence.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9729446B1Protocol-independent packet routing
Publication Date: 2017.08.08 GOOGLE LLC
  • US9729446B1 patent drawing
  • US9729446B1 patent drawing
  • US9729446B1 patent drawing

AI summary

In one aspect, one or more processors may be coupled to a content-addressable memory, a first memory and a second memory. The one or more processors may be configured to receive a data packet, read a predetermined number of bytes from the data packet, and match the read bytes to patterns corresponding to rows of the content-addressable memory. Further, the one or more processors may determine a number associated with the matched row, and based on the number, determine an initial routing instruction. The one or more processors may then determine which bits of the read bytes to hash using hash information stored in the first memory, hash the bits to generate a hash value, determine whether the value corresponds to routing information in the second memory, and route the data packet based on the routing information.