Coupled TCAM and Memory Array Architecture for Reduced Access Time
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional ternary content addressable memories (TCAMs) face challenges in reducing access time during search operations and scaling down the size of TCAM and random access memory (RAM) as technology advances, due to the need for translating match lines into addresses that require decoding by RAM.
Innovation Solution
A compact memory architecture is implemented by tightly coupling TCAMs with a memory array, where the TCAM is divided into two portions on either side of the memory array, with priority logic directly driving the word line of the memory array when a match line is activated, eliminating the need for address translation and utilizing non-volatile memory cells with programmable resistive elements to reduce size and improve access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional TCAM architecture is used with separate address translation, then search functionality is achieved, but access time is increased due to additional decoding steps
Solution Approach 1:
The patent merges the TCAM search functionality with the memory array addressing by directly coupling TCAM match lines to memory array word lines. This eliminates the separate address translation and decoding stage, reducing access time while maintaining search capability. The TCAM and memory array are integrated into a unified structure where the search result directly activates the corresponding memory word line without intermediate address generation or decoding steps.
2Area of stationary object
If TCAM size is reduced for scaling, then device area is minimized, but access time increases due to simplified architecture
Solution Approach 1:
The patent transitions from a two-stage architecture (TCAM + separate address decoder) to a directly coupled single-stage architecture where TCAM match lines are vertically aligned and directly connected to memory array word lines. This dimensional reorganization eliminates the horizontal address translation path, reducing both area and access time by removing intermediate stages while maintaining full search functionality.
3Speed
If volatile memory is used in TCAM, then access speed is improved, but data loss occurs when power is lost
Solution Approach 1:
The patent implements a unified memory architecture where the same memory array serves both as the primary storage and as the TCAM search memory. This multi-functional design allows the system to maintain data in a single location, eliminating the need for separate volatile TCAM structures. The memory array is accessed directly by the coupled TCAM logic, providing both fast access and data retention capabilities in a single integrated structure.
Data Source
AI summary
A memory device includes a first ternary content addressable memory (TCAM), a second TCAM, a memory array coupled to the first and second TCAMs, a first priority logic coupled between the first TCAM and the memory array, a second priority logic coupled between the second TCAM and the memory array, and a look-ahead signal generated by the first priority logic and provided to the second priority logic. Match lines from the first and second TCAMs are coupled to respective word lines in the memory array.