TCAM-Based NFA Accelerator for High-Throughput Regex Matching
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Solution Overview
Problem
Current technologies face challenges in achieving high-throughput, real-time search functions for regular expression matching in networking, cybersecurity, and web services due to the exponential growth of data volume and complexity, requiring efficient hardware acceleration that is scalable and reconfigurable.
Innovation Solution
Implementing ternary content-addressable memory (TCAM) in NFA accelerators, which allows for concurrent processing of multiple characters and runtime reconfigurability, enabling high-throughput regular expression matching by encoding NFAs in CAM and using TCAM tables for efficient pattern matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory structures are used for NFA matching, then device complexity is reduced, but productivity and throughput are insufficient for high-volume data processing
Solution Approach 1:
The NFA matching functionality is segmented into multiple parallel NFA accelerator cores, each capable of independent pattern matching operations. This segmentation enables concurrent processing of multiple characters and patterns simultaneously, thereby increasing throughput while maintaining manageable complexity at each core level.
Solution Approach 2:
Content-addressable memory (CAM) tables are introduced to store NFA transition information, enabling parallel comparison operations across multiple states simultaneously. This dimensional change from sequential memory access to parallel content comparison dramatically increases matching throughput without proportionally increasing control complexity.
2Adaptability or versatility
If fixed hardware structures are used, then device complexity is minimized, but adaptability and reconfigurability are limited for different regular expressions
Solution Approach 1:
The NFA accelerator incorporates runtime reconfigurable CAM tables that can be dynamically updated with different NFA transition information for various regular expressions. This dynamic capability allows the same hardware structure to adapt to different pattern matching requirements without physical reconfiguration, enhancing versatility while maintaining structural simplicity.
Solution Approach 2:
The NFA accelerator core design implements a universal architecture that can match any regular expression by loading appropriate NFA representations into the CAM tables. This multi-functional capability allows a single hardware design to handle diverse pattern matching tasks, improving adaptability without requiring multiple specialized structures.
3Productivity
If parallel processing is implemented to increase throughput, then productivity improves, but device complexity and resource utilization increase
Solution Approach 1:
Multiple NFA accelerator cores are merged into a unified parallel processing architecture that shares common resources such as input data buses and control logic. This merging approach enables concurrent pattern matching while reducing overall resource utilization compared to fully independent cores, thereby improving throughput efficiency.
Solution Approach 2:
The CAM tables are designed to store more transition information than immediately needed, allowing parallel processing of multiple potential matches simultaneously. This excessive storage capacity enables the system to handle uncertain match outcomes in parallel, increasing throughput while the actual resource utilization remains optimized through selective activation of relevant processing paths.
Data Source
AI summary
Systems and methods are provided for using TCAM tables in an NFA accelerator to achieve high throughput regular expression matching, improved scalability, improved resource utilization, and runtime and compile time reconfigurability, while remaining easy-to-deploy (no reliance on specialized hardware) thereby reducing customer barrier-to-entry. The architecture is programmable at runtime due to its dependency on TCAM for its configuration data. Moreover, FPGA gates may be used in the NFA accelerator and may be replaced at runtime using partial reconfiguration to allow limitations in the number of indirection tables and the capacities of the TCAMs to be adjusted at runtime.