Simultaneous Write and Search in Ternary Content Addressable Memory

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Solution Overview

Problem

Conventional TCAM systems face performance limitations due to the need to pause lookup operations while updating rules in memory, which results in inefficiencies and reduced throughput during network traffic adaptations.

Innovation Solution

A TCAM device and method that enable simultaneous write and search operations in a single clock cycle, allowing entry updates to occur in the background while continuing to search other entries, using separate memory write and search buses and circuitry to disable false hits during updates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If lookup operations are paused during memory updates in conventional TCAM systems, then write operations can be performed, but search throughput is reduced and performance is limited

Engineering Contradiction:
Improvesearch throughputVSAvoidlookup operation interruption
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the memory system into multiple independent banks (first bank and second bank) that can operate simultaneously. While one bank is performing write operations, the other bank continues search operations, and vice versa. This segmentation allows parallel execution of write and search operations without mutual interference, resolving the contradiction between maintaining search throughput and performing memory updates.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges write and search operations into the same clock cycle by enabling simultaneous execution in different memory banks. The control logic coordinates both operations to occur concurrently, combining previously separate operational sequences into a unified simultaneous execution model that eliminates lookup interruptions during updates.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If simultaneous write and search operations are enabled, then performance is enhanced and throughput is improved, but device complexity increases due to additional control circuitry

Engineering Contradiction:
Improvepacket classification throughputVSAvoidcontrol circuitry for coordinated operations
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The control logic is designed with multi-functionality to manage both write and search operations simultaneously. It can identify which memory bank requires write operations and which bank can perform search operations, dynamically allocating tasks based on operational state. This universal control approach manages the complexity of coordinated operations while enabling simultaneous execution, resolving the contradiction between enhanced productivity and increased device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If rule updates are performed in background during network traffic adaptations, then adaptability is improved, but false hits may occur during concurrent search operations

Engineering Contradiction:
Improvenetwork traffic adaptationVSAvoidsearch result accuracy
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

By segmenting the memory into separate banks, the patent isolates write operations in one bank from search operations in another bank. This physical separation prevents write operations from interfering with ongoing search operations, eliminating the false hit problem that would otherwise occur during concurrent updates. The segmentation maintains both adaptability for traffic updates and reliability for search accuracy simultaneously.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11557328B2Simultaneous write and search operation in a content addressable memory
Publication Date: 2023.01.17 MEDIATEK SINGAPORE PTE LTD
  • US11557328B2 patent drawing
  • US11557328B2 patent drawing
  • US11557328B2 patent drawing

AI summary

A ternary content addressable memory (TCAM) device comprising an input interface having a first input for receiving first data and a second input for receiving second data; and a memory configured to write the first data into an address selected row of the memory at the same time that a comparison is performed between the second data and at least one other row of the memory different from the address selected row. More particularly, the input interface may further have a third input for receiving a search enable signal and a fourth input for receiving a write enable signal, wherein the memory is configured to write the first data and perform the comparison in response to assertion of the search enable signal at the same time as assertion of the write enable signal. An associated method is also provided.