Packet Processing Acceleration via TCM Prefetching
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Solution Overview
Problem
Existing packet processing devices face performance issues due to cache coherency and cache pollution problems, as well as long latency when accessing direct memory access (DMA) controllers, and replacing DRAM with SRAM increases costs and packet discard rates during network congestion.
Innovation Solution
A device for packet processing acceleration that includes a central processing unit (CPU), a tightly coupled memory (TCM), a buffer descriptor prefetch circuit, and a write back circuit, which eliminates the need for cache memory and direct access to DMA controllers, thereby preventing cache coherency and latency issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache memory is used to improve CPU access speed, then processing performance is improved, but cache coherency and cache pollution problems occur
Solution Approach 1:
The patent extracts the harmful cache coherency and cache pollution problems by eliminating the cache memory component entirely. The TCM is positioned between DRAM and CPU, serving as a dedicated high-speed memory that performs buffer descriptor prefetching and write-back functions without creating cache coherency issues with DMA controllers.
Solution Approach 2:
The TCM acts as an intermediary component between the DRAM and CPU, providing high-speed access to buffer descriptors and packet information. It mediates the data flow by prefetching buffer descriptors from DRAM to TCM, allowing the CPU to process packets without directly accessing slow DRAM, while avoiding the cache coherency problems that would arise from using standard cache memory.
2Speed
If DRAM is replaced with SRAM to improve access speed, then processing performance is improved, but cost increases and packet discard rate increases during network congestion
Solution Approach 1:
The patent applies local quality by providing high-speed access only where needed - specifically for buffer descriptor data that the CPU frequently accesses. The TCM is configured to store buffer descriptors and packet information locally, so the CPU gets fast access to this specific data without requiring the entire system to use expensive SRAM. This selective approach maintains performance while controlling cost.
Solution Approach 2:
The memory system is segmented into different functional areas: DRAM stores bulk packet data and buffer descriptors, while TCM stores a subset of buffer descriptors and packet information for fast CPU access. This segmentation allows the system to use cost-effective DRAM for bulk storage while providing high-speed access paths for critical data through TCM, avoiding the need to replace all DRAM with expensive SRAM.
3Measurement precision
If CPU directly accesses DMA controller indices to improve packet processing, then processing accuracy is improved, but latency increases
Solution Approach 1:
The TCM performs preliminary action by prefetching buffer descriptors from DRAM to TCM before the CPU needs to process them. The prefetch circuit continuously loads buffer descriptor data into the TCM in advance, so when the CPU needs to access packet information, the data is already available in the high-speed TCM, eliminating the latency that would result from direct DRAM access while maintaining accurate packet processing.
Data Source
AI summary
A device for packet processing acceleration includes a CPU, a tightly coupled memory (TCM), a buffer descriptor (BD) prefetch circuit, and a BD write back circuit. The BD prefetch circuit reads reception-end (RX) BDs from an RX BD ring of a memory to write them into an RX ring of the TCM, and reads RX header data from a buffer of the memory to write them into the RX ring. The CPU accesses the RX ring to process the RX BDs and RX header data, and generates transmission-end (TX) BDs and TX header data; afterwards, the CPU writes the TX BDs and TX header data into a TX ring of the TCM. The BD write back circuit reads the TX BDs and TX header data from the TX ring, writes the TX BDs into a TX BD ring of the memory, and writes the TX header data into the buffer.