TCON I2C Clock Synchronization for Stable External Memory Access
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Solution Overview
Problem
In liquid crystal displays, the lack of data synchronization between the I2C master and external memory leads to signal delays and transmission errors, affecting the driving of the display due to unsupported synchronization in existing TCON designs.
Innovation Solution
A TCON circuit with a pre-scaler that determines clock signal synchronization and stops transmission if not synchronized, using a noise filter for the external memory's clock signal, allowing for a stable data latch in an asynchronous interface by ensuring the external memory is ready to transmit data before initiating the I2C interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the I2C master transmits data to external memory using a simple clock signal without synchronization control, then the device complexity is reduced, but data transmission errors occur due to lack of synchronization between master and slave clock signals
Solution Approach 1:
The patent implements a feedback mechanism where the I2C master monitors the readiness status of the external memory and adjusts its data transmission timing accordingly. The master waits for confirmation that the memory is ready before transmitting data, ensuring synchronization without requiring complex hardware modifications to the I2C interface itself.
Solution Approach 2:
The patent employs preliminary action by having the I2C master send a command signal to the external memory before data transmission to check readiness status. This preliminary check ensures that the memory is prepared to receive data, preventing synchronization errors without adding complex synchronization hardware.
2Reliability
If the I2C master waits for external memory readiness before data transmission, then data transmission reliability is improved, but transmission time increases due to waiting periods
Solution Approach 1:
The patent maintains continuity of useful action by implementing a loop that continuously checks the readiness status of the external memory. Instead of idle waiting, the master actively monitors the memory status register in successive cycles, ensuring that data transmission begins immediately when the memory becomes ready, thus minimizing unnecessary delays.
Solution Approach 2:
The patent applies the skipping principle by rapidly checking the memory readiness status in successive clock cycles. When the memory becomes ready, the master immediately proceeds with data transmission without unnecessary delays, effectively rushing through the waiting period by utilizing every available clock cycle for status monitoring.
3Device complexity
If the I2C interface operates without noise filtering on clock signals, then the device complexity is reduced, but synchronization accuracy deteriorates due to noise interference
Solution Approach 1:
The patent introduces an intermediary noise filter circuit in the signal path between the I2C master and external memory. This filter acts as a mediator that cleans the clock signals of noise and interference before they reach the receiving端, improving synchronization accuracy without requiring complex digital signal processing or modification of the I2C protocol.
Data Source
AI summary
A method of controlling an interface between an I2C master in a time controller for a liquid crystal display and an external memory may include causing a pre-scaler to determine whether or not a first clock signal from the I2C master to the external memory is synchronized with a second clock signal from the external memory to the I2C master. If the first clock signal is not synchronized with the second clock signal, the pre-scaler stops transmission of a third clock signal for an I2C interface with the external memory to the I2C master.