Tcon Board IIC Collision Prevention via Detection Circuit

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Solution Overview

Problem

Current display devices face data collision issues between the Timing Controller (Tcon) board and the System on Chip (SoC) due to bidirectional Inter-Integrated Circuit (IIC) communication, leading to random data overwriting and potential chip overwriting, especially in high-resolution and high-refresh-rate displays with multiple chips.

Innovation Solution

A detection circuit on the Tcon board and a switching circuit on the main control board are implemented, using a flexible flat cable to communicate through specific signal pins, where the detection circuit outputs a second level signal to stop the main control board from sending data when a data collision is detected, preventing IIC data collisions by setting the IIC to a high level.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If bidirectional IIC communication is implemented between Tcon board and SoC, then data transmission functionality is improved, but data collision risk increases

Engineering Contradiction:
Improvedata transmission functionalityVSAvoiddata collision risk
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The detection circuit detects the data signal level from the Tcon board in advance before the SoC sends data through the IIC bus. When a data signal is detected, the switching circuit proactively sets the IIC to high level to prevent collision before it occurs, rather than reacting after collision happens.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The switching circuit acts as an intermediary between the SoC and the IIC bus. It receives control signals from the detection circuit and uses them to mediate the data transmission by setting the IIC to high level when Tcon board sends data, thereby controlling access to the bus and preventing direct collisions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multiple chips are added to Tcon board for high-resolution high-refresh-rate display, then display performance is improved, but number of IIC paths increases

Engineering Contradiction:
Improvedisplay performanceVSAvoidnumber of IIC paths
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The detection circuit and switching circuit are designed to work with multiple IIC paths universally. The detection circuit can detect data signals from any of the multiple chips, and the switching circuit can control any of the multiple IIC paths, making the collision prevention mechanism applicable to all chips without requiring separate solutions for each.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If detection circuit and switching circuit are added to prevent data collision, then data transmission reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The detection circuit automatically detects the data signal level from the Tcon board without requiring external intervention. The switching circuit automatically responds by setting the IIC to high level when data is detected, creating a self-service collision prevention mechanism that operates autonomously based on the detected signal conditions.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11600220B2Timing controller board, main control board, display device, and detection method thereof
Publication Date: 2023.03.07 HEFEI BOE DISPLAY TECH CO LTD
  • US11600220B2 patent drawing
  • US11600220B2 patent drawing
  • US11600220B2 patent drawing

AI summary

The disclosure discloses a timing controller board, a main control board, a display device and a detection method thereof. The timing controller board outputs a second level signal transmitted by a first fixed potential signal pin to the main control board through a detection circuit when a first data signal pin outputs a first level signal; the main control board loads a second potential signal transmitted by a second fixed potential signal pin to a second data signal pin and a clock signal pin through a switching circuit upon receiving the second level signal, to cause the main control board to stop sending a data signal to the timing controller board through the second data signal pin and stop sending a clock signal to the timing controller board through the clock signal pin.